South Korea initiates major R&D project to boost chips packaging competitiveness

Lin Yu-chun; Willis Ke, DIGITIMES Asia 0

Credit: AFP

Recognizing the strategic importance of semiconductor packaging technology, the South Korean government is reportedly initiating a major packaging technology R&D project aimed at assisting companies in quickly catching up with international leaders like TSMC in the advanced packaging field, and the project will be headed by a former CEO of Amkor Korea.

South Korean news media outlet The Elec cited sources from the Ministry of Trade, Industry and Energy (MOTIE) and the Korea Evaluation Institute of Industrial Technology as indicating that the "Semiconductor Advanced Packaging Leading Core Technology Development Project" will cost between KRW300–500 billion (US$234–390.6 million) over a period of 5–7 years. The planning process is being helmed by Park Yong-chul, former CEO of Amkor Korea, who has chaired the promotion committee for the project.

The advanced package R&D project can be broadly categorized into two types: catch-up and lead. The former aims to boost domestic capabilities in areas such as heterogeneous integration, wafer-level package (WLP), panel level package (PLP), and high-density flip chip. These areas are currently dominated by Taiwan's TSMC, America's Amkor, and China's JCET group. Among them, TSMC excels in the area of high-density SoC technology, and by leveraging its strengths in technologies such as fan-out wafer-level packaging (FOWLP), chip integration, and 2.5D packaging, it has secured significant orders from major US tech players like Apple, Nvidia and AMD.

As to the lead type, it will concentrate on technology segments where South Korean companies have demonstrated prowess, such as 2.5D package-based high-bandwidth memory (HBM) optimization, 10 to 40 micrometer (µm) bonding, and hybrid bonding, with the latter being particularly high profile lately, especially in the context of Nvidia's H100 AI GPU.

It is reported that the R&D project has reached the final drafting state and will soon undergo a preliminary review, but industry players are calling for the review process to be exempted or simplified in order for South Korean semiconductor players to faster enhance their chips packaging competitiveness.

In related development, Yonhap News Agency has recently reported that South Korea's Electronics and Telecommunications Research Institute (ETRI) has developed an advanced semiconductor chiplet packaging technology that can save 95% of power consumption compared with the current Japanese technology. ETRI has achieved this by utilizing its newly developed materials and lasers, reducing the manufacturing process from nine to three stages, and the advancement holds promise for future applications in high-performance AI chips for self-driving vehicles and datacenters.

The new technology involves applying a non-conductive thin film (NCF) onto a semiconductor wafer, with the film made from a novel material developed by ETRI. Subsequently, chiplets are placed onto the wafer and then subjected to a broad area laser beam exposure for just one second. The entire process consists of only three stages, similar to stacking LEGO blocks on a semiconductor substrate.

Currently, semiconductor manufacturers primarily utilize materials from Japan in their advanced packaging processes. Due to the complexity of the manufacturing, involving nine stages and multiple pieces of equipment, there are various drawbacks, including high power consumption, high cleanroom maintenance costs and emissions of toxic substances.

When ETRI's newly developed material is irradiated with laser light, it can simultaneously address multiple stages in the semiconductor packaging process such as bonding, cleaning, drying, coating, and curing. This simplification of the process leads to a significant reduction in production facilities, from over 20 meters to four meters. Additionally, the process doesn't require nitrogen gas, thereby avoiding the generation of toxic substances, and it can also be conducted directly at room temperature of 25 degrees Celsius.

According to ETRI, the new chiplet packaging technology will be commercialized within three years at the earliest.