AI and high-performance computing chip demand continue to expand, keeping TSMC's CoWoS capacity tight into 2026. The supply constraint is pushing Taiwan's major OSAT providers, including ASE Holdings, SPIL and PTI Group, to accelerate advanced packaging expansion to secure AI-related orders.
Panel race heats up
Fan-out panel-level packaging (FOPLP) has become a central focus for backend suppliers. By moving from round wafers to square panels, the process lowers unit costs and addresses high-end AI chip packaging demand. Industry assessments remain positive — although vendors adopt different panel sizes, panel-level packaging technologies are expected to reach mass production as early as 2027.
PTI Group has moved ahead of its peers in panel-level packaging. Its 510mm x 515mm panel format has gained support from customers including AMD and Broadcom. In 2026, the company launched an NT$43.3 billion (US$1.38 billion) investment plan focused on FOPLP, targeting mass production in the first half of 2027.
TSMC's CoPoS shift reshapes the field
TSMC has also reassessed its advanced packaging roadmap, prioritizing CoWoS capacity expansion over the next two years. This shift has renewed industry attention on its in-house panel-level packaging technology, CoPoS — and supply chain sources indicate the move may affect ASE Holdings' strategy, as the company aligns around a 310mm x 310mm panel specification for its FOPLP capacity planning.
ASE sets its 2026 automation target
ASE Holdings COO Tien Wu said AI compute demand is accelerating heterogeneous integration and driving larger package sizes. The group aims to complete a fully automated 310mm x 310mm production line by the end of 2026 and then begin pilot production. Wu noted that one FOPLP line is already in place, but without full automation it cannot achieve the scale efficiencies the market requires.
On the possibility of expanding the panel size to 620mm x 620mm, ASE Holdings said decisions will depend on customer demand, chip design specifications and yield performance.
ASE Holdings COO Tien Wu. Credit: DIGITIMES
A decade in the making
ASE Holdings has invested in FOPLP for more than 10 years. It initially adopted a 300mm x 300mm panel format and currently operates a production line at that size, mainly serving power management ICs and automotive chips. As AI chips began requiring larger panel formats, ASE expanded to 600mm x 600mm and announced a US$200 million investment to build its first mass-production line in Kaohsiung. It later reduced the panel size to 310mm x 310mm to align more closely with TSMC's CoPoS approach, expecting this specification to become mainstream.
Article edited by Jerry Chen
