Adoption of copper pillar bump for flip-chip (FC) packaging is expected to increase, with its proportion rising from 10-20% in 2010-2011 to 20-30% in 2015, industry sources quoted unnamed market research firms as saying.
Copper pillar bumping will replace conventional solder bumping as the mainstream FC packaging technology, as the new method offers cost savings and achieves a higher memory density, the sources indicated.
Chip vendors, particularly those specializing in handset solutions, consider copper pillar bump a low-cost alternative, when they migrate to 28nm and smaller-geometry processes, the sources said. The migration is meant to reduce further their manufacturing costs, the sources added.
Texas Instrument (TI), for instance, has partnered with IC packager Amkor Technology to use copper pillar FC packages for products at the 45nm node and below. TI's solution processed with copper pillar bumping has been adopted for Amazon's Kindle Fire media table, the sources pointed out.
ST-Ericsson is also looking to adopt copper pillar FC packages in its chip devices built using 28nm and below node processes in 2012, the sources said. With vendors making a major push, the transition to the new FC packaging technology will be speeding up.
In view of the trend, major Taiwan-based IC backend houses Advanced Semiconductor Engineering (ASE), Siliconware Precision Industries (SPIL) and Powertech Technology (PTI) reportedly have all stepped up development of their copper pillar bumping technologies.
In addition, contract chipmaker Taiwan Semiconductor Manufacturing Company (TSMC) reportedly is offering high-end packaging services such as FC chip-scale package (CSP) and wafer-level CSP for its clients, including the new copper pillar FC package, according to the sources. The backend business contributes less than 5% to TSMC's total revenues at present, the sources added.
Article translated by Jessie Shen
