Intel CEO Pat Gelsinger will visit TSMC in Taiwan in November, according to industry sources, who also believe that recent media claims about TSMC withdrawing the Intel discount are ludicrous.
As the critical moment of the US presidential election nears, numerous remarks and strategic goals are being excessively construed, especially regarding the competitive dynamics of semiconductors linked to political matters. Export limitations enacted by the US, together with issues pertaining to TSMC and Intel, have emerged as significant topics of discourse.
Amidst several predictions, the imminent travel of Gelsinger to Taiwan to confer with TSMC Chairman and CEO C. C. Wei appears more plausible.
A significant discount for Intel? Why should it
TSMC would not grant Intel a 40% discount while demand for its 3nm capacity exceeds supply, the sources indicated. Reports that Gelsinger openly criticized certain aspects of TSMC, which may have prompted the contract chipmaker to remove the previously agreed-upon 40% wafer fabrication discount, are unfounded.
Given that Intel is not as close to TSMC as Apple, providing Intel a big discount during a period of high demand appears unlikely, the sources said. The collaboration between TSMC and Intel is less stable than that with long-term large customers such as Apple.
While discounts are not included in Intel's outsourcing of orders to TSMC for 3nm processors, there are indications that TSMC has raised prices, according to the sources.
TSMC is carefully considering strategies to mitigate the impact of mass production and capacity expansion of 3nm process technology, which may have a negative impact on gross margins, as well as the ongoing increase in electricity prices, inflationary pressures, and the significant costs associated with building overseas facilities. Thus, TSMC is eager to raise 3nm foundry prices, and it is unlikely that Intel will receive a significant discount given the tight supply of 3nm production capacity, according to the sources.
Frequent delays in Intel's 3nm chip orders
Intel's plan to place significant 3nm chip orders with TSMC had been discussed for two to three years, and the fulfillment of these orders was frequently postponed, even after they were confirmed, according to industry sources.
Initially, Intel planned to depend mostly on its own 20A and 18A processes, with some components of the Lunar Lake and Arrow Lake processors using TSMC's first-generation N3B process to reduce risks and meet launch dates. However, due to continued challenges with Intel's processes and yields, the company was forced to switch wholly to TSMC for manufacturing, the sources said.
The newly unveiled Lunar Lake comprises two primary chip blocks: the compute tile and the I/O tile. It utilizes Intel's Foveros advanced packaging technology and incorporates memory interconnects. The computing tile employs TSMC's N3B process, including the new E-core and P-core microarchitectures, alongside the Xe2 GPU architecture, NPU 4, and image processing unit (IPU). The I/O tile is fabricated utilizing TSMC's 6nm manufacturing technology.
Due to the near-total allocation of N3B capacity to Apple and TSMC's expedited transition to the enhanced N3E capacity, Intel is compelled to accept elevated prices to ensure prompt production, according to the sources.
TSMC's capacity allocation has been negatively impacted by recurrent delays in Intel's ordering schedule. The customer's sudden decision to boost orders necessitates the reallocation of resources to meet unforeseen demands, incurring additional costs that it must bear, the sources said.
Furthermore, the initial development of TSMC's 3nm technology was conducted in collaboration with Apple to validate order volumes before estimating wafer starts for additional customers and finalizing capacity planning, similar to previous technological advancements in 5/7nm processes. Discounts are generally designated for large customers, such as Apple, who participate in joint development and place substantial advance orders, the sources indicated.
The current N3B capacity is exclusively reserved for Intel, as Apple has fully embraced the N3E process. Intel is seeking to prevent price increases for TSMC's N3 process, which is scheduled for 2025, according to the sources.
What issues will be discussed when Gelsinger meets Wei?
Industry sources have observed that Intel intends to concentrate on its proprietary 18A process. The next generation PC processor Panther Lake will not be wholly outsourced to TSMC; some or all computer chip blocks will be manufactured in-house.
Gelsinger recently claimed that Panther Lake samples were already given to Lenovo. Intel 18A has also been awarded a contract by Amazon Web Services.
Nonetheless, the supply chain perceives the yield rate for the 18A process as questionable, suggesting that Intel may ultimately need to revert to TSMC for support, so limiting the 18A process to the production of its high-end server processors, Xeon.
Fresh speculation suggests that Gelsinger will meet with Wei at TSMC headquarters in November to discuss crucial concerns such as lowering current N3B foundry prices and obtaining critical N3E capacity for the upcoming "Falcon Shores" AI GPU, which is scheduled for release by the end of 2025. This will need competing for capacity with other major players such as Apple, Qualcomm, MediaTek, AMD, and Nvidia in both advanced manufacturing and packaging technologies, according to the sources.
Due to slower-than-expected progress with its own 14A technology, Intel is also trying to reserve 2nm capacity from TSMC, the sources said.
Wei remarked at TSMC's investors meeting in mid-October that customer demand for 2nm technology presently outstrips that for 3nm technology, implying that predicted capacity will be even higher.
Article translated by Jessie Shen
