Following the US sanction updates against Chinese semiconductor development on October 17, which established Total Processing Performance and Performance Density as the new parameters to restrict Chinese advanced computing and AI developments, China's advanced packaging and chiplet sectors have also come under radar. As the Bureau of Industry and Security (BIS) pointed out, the performance density parameter prevents China from circumventing restrictions by "simply purchasing a larger number of small datacenter AI chips which, if combined, would be equally powerful as restricted chips."
Pursuing Moore's Law will lead to performance gap
Not surprisingly, the move has pushed Chinese semiconductor industry to accelerate the development of an indigenous chiplet ecosystem. During a October 25 event hosted by Xpeedic Technology, a Shanghai-based EDA and SiP design solution provider, industry representatives convened to examine the current state of Chinese chiplet development.
Noting the recent surge of generative AI and large language models (LLM), Lin Feng, founder and CEO of Xpeedic, indicated that if Chinese semiconductor development merely follows the path of Moore's Law, there will be a major performance gap to meet the need of AI computing. "We wouldn't be able to address the gap through increasing transistor density or packaging density, as it requires solution at a deeper level," said Lin, who believes that traditional system on a chip (SoC) is giving way to System of Chiplets, thus leading to better yields, lower costs, shorter time to market, and overcoming lithography reticle limit. Noting the success cases of AMD and Apple's chiplet developments, Lin regards "EDA + IP + Packaging" to be the formula of success in the sector.
Interconnect standard fundamental, but co-design is the real key
Wu Feng, a chief engineer from ZTE Corp specialized in high-speed interconnect technology, in turn highlighted the three current barriers faced by Chinese chiplet development, including that it cannot replace advanced processing technology, its interconnect standard needs further standardization, and its costs have to improved. The ZTE engineer also pointed out that packaging, die-to-die (D2D) interconnect and system-level co-design are the key chiplet technologies to be strengthened, especially when it comes to D2D standardization efforts that are deemed fundamental to ecosystem building. Though D2D standardization and packaging are foundational, Feng believes that chiplet architecture and the realization of design are the true keys to Chinese chiplet industry's competence, especially chiplet co-design, simulation and verification. In this context, a corresponding EDA ecosystem is a key battleground.
At the event, Yao Li, head of Unisoc's packaging design department, also showcased the company's ambition to use chiplet platform on multiple applications, including smartphones, automotive dual-channel modules, automotive Flip-Chip Ball Grid Array (FCBGA), and display FCBGA. In terms of various advanced packaging technologies, Yao observes that the consumer electronics sector in China often require Flip Chip Chip Scale Packaging (FCCP) and Wafer Level Chip Scale Package (WLCSP). In comparison, industrial applications mainly require SiP and FCBGA.
Reference points for future breakthrough?
Regarding China's path forwards amid the latest US sanctions, Yin Shouyi, Vice Dean of Tsinghua University's School of Integrated Circuits, summarized several different ways of chip innovation merging computing architecture and advanced packaging. Yin mentioned several efforts as reference points for such endeavors, including the dataflow processing chip represented by Google TPU and Samsung's effort to integrate Processing-in-Memory (PIM) and High Bandwidth Memory (HBM), Yin also referred to wafer-level chips such as Tesla Dojo, and Intel's 3D-stacked Ponte Vecchio as references for Chinese advanced packaging development.
