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CoWoS, SiP to be key packaging processes for AI chips
Nobunaga Chai, DIGITIMES Research, Taipei

High performance computing (HPC) will become the most crucial platform in the development of process technologies for AI (artificial intelligence) chips, and CoWoS (chip on wafer on substrate) and SiP (system in package) will emerge as key packaging processes for such chips, according to Digitimes Research.

Usually, an AI architecture will include the upstream cloud computing, midstream edge computing and downstream devices. And the performance of AI chips can be boosted by upgrading the microform technology and changing the transistor structure in the front end, or by incorporating advanced packaging technologies in the back end.

In the backend packaging, the 2.5D CoWoS process technology launched by Taiwan Semiconductor Manufacturing Company (TSMC) can upgrade the performance of packaged ICs by sharply boosting I/O pin numbers through the incorporation of silicon interposer and the TSV (through si via) technology. In the first half of 2017, TSMC launched an HPC platform using 7nm CoWoS process technology to further better IC performance.

In addition, the IoT platform also plays an important role in AI development. As IoT chips involve requirements for low power consumption, low cost and ready availability, SiP will be the main packaging technology applicable to chip solutions for IoT applications.

Accordingly, it will be an increasingly important trend for chipmakers to integrate frontend and backend process technologies, Digitimes Research believes, adding that makers must join forces with EDA, IP, and IC designers to build a complete ecosystem if they want to secure a preemptive presence in the AIoT (artificial intelligence IoT) space.

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