Japan's LSTC backs up Rapidus' 2nm ambition with multinational team

Chiang, Jen-Chieh, Taipei, DIGITIMES Asia 0

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The Leading-edge Semiconductor Technology Center (LSTC) established by the Japanese government, along with Rapidus, was formed in 2022, marking a crucial initiative for Japan's advancement in chip manufacturing. LSTC spearheads the research and development while Rapidus handles production.

According to reports from Nikkei and Munavi, in February 2024, LSTC received funding from the New Energy and Industrial Technology Development Organization (NEDO) under the Ministry of Economy, Trade, and Industry of Japan, amounting to a maximum of JPY45 billion (approximately US$300 million), allocated for research and development in two projects.

These projects include research into semiconductor manufacturing technologies below 2 nanometers and with short Turn Around Time (TAT), with a budget of JPY17 billion. Another project aims to facilitate the easier integration of cutting-edge chips into terminal designs, with a budget of JPY28 billion. Both projects are slated to continue until 2029, operating over a span of five years.

Regarding the research and development of manufacturing technologies below 2 nanometers and short TAT, LSTC focuses on developing materials and equipment necessary for GAA (Gate-All-Around) process technology for chips below 2 nanometers, as well as techniques to shorten lead time.

Key participants in this R&D initiative include Rapidus, targeting mass production of 2-nanometer chips, as well as organizations such as the National Institute of Advanced Industrial Science and Technology (AIST), the University of Tokyo, Tohoku University, and Tokyo Institute of Technology. Collaborating institutions include Yokohama National University and several other universities.

Additionally, certain aspects of this research are subcontracted to multinational companies. Subcontractors include subsidiaries of Applied Materials and GlobalWafers in Japan, Sumco, Kioxia, and AI unicorn Preferred Networks (PFN).

International collaboration partners include Applied Materials, imec in Belgium, and CEA-Leti in France.

In the second project, focusing on design techniques for the application of cutting-edge chips, LSTC targets AI processing in edge devices, enabling robots and other terminals to perform AI computations autonomously with low latency, without relying on the cloud.

Participants in this aspect of the project include AIST, the University of Tokyo, Rapidus, and AI chip startup Tenstorrent.

Tenstorrent and Rapidus signed an MOU in 2023 to collaborate on developing silicon intellectual property (IP) for edge AI components incorporating 2-nanometer logic ICs. Now, with funding from NEDO, LSTC has joined this research and development endeavor.

Apart from the development of 3DIC architectures, a software development platform comprising compilers, libraries, and simulators is required, including standard software using AI libraries such as TensorFlow and PyTorch.

Furthermore, integrating cutting-edge semiconductors into terminals requires IP to design logic circuits that are both suitable for application and cost-effective. Due to the scarcity of talent in the field of hardware-software integration, LSTC must also focus on nurturing relevant expertise.