Advanced Semiconductor Engineering (ASE) and Cadence Design Systems have collaborated to release a system-in-package (SiP) EDA solution that addresses the challenges of designing and verifying fan-out chip-on-substrate (FOCoS) multi-die packages, according to the companies.
The solution consists of Cadence' SiP-id (intelligent design) design kit, an enhanced reference flow including IC packaging and verification tools from the company, and a new methodology that aggregates the requirements of wafer-, package- and system-level design into a unified and automated flow. By deploying Cadence' SiP-id methodology, designers can reduce design iterations and greatly improve throughput as compared to existing advanced packaging EDA tools, reducing the time needed to design and verify ultra-complex SiP packages.
Previously, IC packaging engineers leveraged standard EDA design tools coupled with a set of loosely defined rules to lay out their packages. However, this approach has many limitations when designing today's advanced multi-die packages. To provide a more holistic approach to the design and verification of SiP and advanced fan- out packages, ASE and Cadence collaborated closely to develop a design kit, methodology, and streamlined and automated reference flow using enhanced Cadence IC packaging and verification tools, all tailored for ASE's advanced IC package technologies. In a typical use case with high-pin-count dies, packaging engineers using SiP-id and the accompanying reference flow and methodology were able to reduce time from more than six hours to only 17 minutes, compared to existing tools with manual operation.
"ASE has been augmenting our design and manufacturing services by building a SiP ecosystem with partners across the entire supply chain including EDA providers," said CP Hung, VP of corporate R&D for ASE Group. "SiP-id is a prime example of the successful collaboration between ASE and Cadence that achieved optimal results through the mutual sharing of technology and experiences."
"Advanced packaging extends Moore's Law and plays directly into our System Design Enablement strategy, so collaborating with ASE to fulfill their vision for SiP is a natural fit for us," said Tom Beckley, senior VP and GM of Cadence' custom IC & PCB group. "We expect the results of this effort to mutually benefit Cadence and ASE customers by providing a methodology optimized for SiP design."
SiP-id is immediately available from ASE.
