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NEWS TAGGED WAFER-LEVEL PACKAGING
Monday 14 November 2016
Fujifilm to open new plant for advanced IC materials in Taiwan
Fujifilm has announced that its semiconductor business subsidiary, Fujifilm Electronic Materials, will launch the operation of its third plant in Taiwan in late November. The new...
Wednesday 26 October 2016
ASE ready to enter volume production of fan-out wafer-level packaging
Advanced Semiconductor Engineering (ASE) has reportedly obtained orders for fan-out wafer-level packaging (FOWLP) from Qualcomm, MediaTek and HiSilicon with volume production set...
Wednesday 28 September 2016
PTI buys wafer-level packaging equipment
Packaging and testing company Powertech Technology has purchased wafer-level packaging equipment from Ultratech SE Asia for NT$544 million (US$17 million), according to a company...
Tuesday 20 September 2016
Applied Materials, IME to advance R&D in fan-out wafer-level packaging
Applied Materials and the Institute of Microelectronics (IME), a research institute under Singapore's Agency for Science, Technology and Research, have announced a five-year extension...
Wednesday 11 May 2016
STATS ChipPAC fan-out wafer-level packaging shipments exceed 1 billion units
STATS ChipPAC has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded wafer-level ball grid array (eWLB), according to the company...
Thursday 28 April 2016
Cypress subsidiary Deca to receive US$60 million investment from ASE
Advanced Semiconductor Engineering (ASE) and Deca Technologies, a subsidiary of Cypress Semiconductor, have announced the signing of an agreement whereby ASE will invest US$60 million...
Wednesday 16 March 2016
Cadence launches complete IC packaging design and analysis solutions for fan-out WLCSP
Cadence Design Systems has announced the availability of foundry-proven IC packaging design and analysis solutions for advanced fan-out wafer-level chip scale packaging (WLCSP) and...
Monday 18 January 2016
TSMC expects to launch 5nm node 2 years after 7nm
TSMC will be ready to roll out its 5nm process technology two years after the launch of its 7nm node, according to the pure-play foundry.
Tuesday 15 December 2015
Advanced semiconductor packaging drives materials consumption through 2019, says SEMI
The US$18 billion semiconductor packaging materials will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC...
Friday 11 December 2015
TSMC to provide backend InFO packaging technology for Apple chips, says report
TSMC is scheduled to move its integrated fan-out (InFO) wafer-level packaging technology to volume production in the second quarter of 2016. Apple will be among the first wave of...
Wednesday 23 September 2015
Cadence offers design tools for TSMC InFO packaging
Cadence Design Systems has announced that its Allegro system-in-package (SiP) and physical verification system (PVS) implementation technologies have been enabled for TSMC's integrated...
Thursday 18 June 2015
NANIUM enables WLCSP without UBM
NANIUM S.A., a leading provider of advanced semiconductor packaging known for its innovative solutions, today announced it achieved outstanding reliability results for a Wafer-Level...
Thursday 21 May 2015
Xintec profits soar in 1Q15
Taiwan's Xintec, an affiliate of Taiwan Semiconductor Manufacturing Company (TSMC) specializing in packaging services for CMOS image sensors as well as MEMS and fingerprint sensors,...
Tuesday 5 May 2015
TSMC InFO-WLP technology to generate significant revenues starting 2016
Taiwan Semiconductor Manufacturing Company's (TSMC) backend integrated fan-out (InFO) wafer-level packaging (WLP) technology will start contributing significantly to the IC foundry's...
Tuesday 7 April 2015
Altera, TSMC develop UBM-free WLCSP packaging
Altera and TSMC have produced an UBM-free (under-bump metallization-free) WLCSP (wafer-level chip scale package) technology for Altera's MAX 10 FPGA products, according to the comp...