72 news items tagged wafer-level packaging
Xintec 12-inch wafer-level CSP ready for volume production in 2H15, says chairman
Tuesday 17 March 2015
Image sensor packaging house Xintec will have its 12-inch wafer-level chip-scale package (WL-CSP) line ready for volume production in the second half of 2015, according to company...
TSMC to offer InFO-WLP technology for 16nm chips, eyeing Apple orders
Wednesday 4 February 2015Taiwan Semiconductor Manufacturing Company (TSMC) will have its backend integrated fan-out (InFO) wafer-level packaging (WLP) technology ready for 16nm chips, eyeing orders for Apple's...
UTAC said to set up 12-inch wafer-level packaging line in Taiwan
Tuesday 23 December 2014United Test and Assembly Center (UTAC), a Singapore-based assembly and test company, will continue its investment in Taiwan in 2015 by setting up a 12-inch wafer-level packaging line,...
High-end packaging next battlefield for IC assembly and test services providers, says Amkor executive
Tuesday 9 July 2013
Robust growth in smartphone usage is encouraging semiconductor assembly and test services providers to head towards related packaging technologies. Amkor Technology is already among...
STATS ChipPAC to pump another US$500 million into expansion in Singapore
Wednesday 29 May 2013STATS ChipPAC has unveiled plans to invest another US$500 million to expand its operations in Singapore, where the IC backend house is headquartered.
Scientech deepens development of 3D IC, wafer-level packaging equipment
Thursday 31 January 2013Taiwan-based semiconductor equipment distributor Scientech has deepened its development of 3D IC packaging and wafer-level packaging equipment, expecting some of its equipment to...
ChipMOS expects sales growth in 2012
Monday 19 March 2012Packaging and testing firm ChipMOS Technologies has forecast consolidated revenues for 2012 will increase 10%. The company revealed that net revenues on a US GAAP basis for 2011 grew...
Aptos expanding 12-inch wafer level packaging business
Wednesday 14 March 2012Aptos Technology, which specializes in backend services for the production of NAND flash chips and devices such as microSD cards, announced March 13 that two of its subsidiaries will...
STATS ChipPAC intros new 3D eWLB PoP solutions
Wednesday 7 March 2012STATS ChipPAC, a semiconductor test and advanced packaging service provider, has announced its next-generation three dimensional (3D) embedded wafer-level ball grid array (eWLB) package-on-package...
STATS ChipPAC breaks ground for new factory
Friday 6 January 2012STATS ChipPAC on January 5 hold a groundbreaking ceremony for its new factory in Singapore, according to the chip test and packaging service provider. The new 197,000-square foot...
Focus on small, cost-effective packages: Q&A with STATS ChipPAC CEO Tan Lay Koon
Monday 21 November 2011
Despite uncertainties in the semiconductor industry outlook, packaging and testing firm STATS ChipPAC will continue investing in advanced IC packages for space-critical designs that...
STATS ChipPAC to open new wafer-level packaging plant in Taiwan, says paper
Monday 14 November 2011STATS ChipPAC is scheduled to hold an inauguration ceremony for a 12-inch wafer bumping and wafer-level packaging plant in Hsinchu County, northern Taiwan, Thursday (November 17),...
PTI developing advanced packaging technologies
Friday 1 July 2011Packaging and testing firm Powertech Technology (PTI) expects the development of new technologies including wafer-level packaging, 3D IC packaging and copper pillar bumping to bear...
ASE aims at global market share of 25-30% in 2014
Wednesday 29 June 2011IC packaging/testing service provider Advanced Semiconductor Engineering (ASE) aims to hike its global market share from 17-18% in 2010 to 25-30% in 2014, COO Tien Wu said at the...
STATS ChipPAC expands WLP offering with 12-inch manufacturing in Taiwan
Tuesday 18 January 2011STATS ChipPAC has announced the expansion of its wafer-level package (WLP) offering with new 300mm manufacturing capabilities in Taiwan. The 300mm WLP operation is located in Hsinchu...
ASE to budget US$700 million in capex for 2011, says paper
Monday 4 October 2010IC packaging and testing house Advanced Semiconductor Engineering (ASE) plans to budget US$700 million in capex for 2011, flat on year, an unnamed company executive has been cited...
STATS ChipPAC opens new plant for 300mm eWLB wafer manufacturing
Wednesday 15 September 2010STATS ChipPAC on September 15 celebrated the opening of a new manufacturing facility to process 300mm wafers using embedded wafer-level BGA (eWLB) technology. The Singapore-based...
SPIL enters LED packaging market
Tuesday 14 September 2010Siliconware Precision Industries (SPIL) has entered the LED packaging business and started LED shipments through wirebonding packaging technology to three US-based clients. It is...
Aptos invests in ACE to enhance wafer-level package offering
Monday 30 November 2009Aptos Technology, a 20%-held packaging and testing affiliate of Phison Electronics, has announced it recently acquired an 87% stake in wafer-level packaging (WLP) house Advanced Chip...
Plant fire at KYEC affiliate ACE, reports paper
Wednesday 7 October 2009Advanced Chip Engineering (ACE), a wafer-level packaging and testing house which has investment from King Yuan Electronics Company (KYEC), suffered a fire on the second floor of a...
STATS ChipPAC expanding capacity for wafer-level packaging
Wednesday 17 June 2009STATS ChipPAC has announced it is expanding capacity for full turnkey wafer-level packaging in its Singapore operation. The IC packaging and testing service provider said it is on...
Integrated handheld solutions driving demand for wafer-level packaging, says ASE
Monday 13 April 2009Handheld devices incorporating functionality such as Bluetooth, FM radio, GPS and Wi-Fi have become the market driver for wafer-level packaging (WLP), Taiwan's Advanced Semiconductor...
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