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NEWS TAGGED WAFER-LEVEL PACKAGING
Wednesday 29 May 2013
STATS ChipPAC to pump another US$500 million into expansion in Singapore
STATS ChipPAC has unveiled plans to invest another US$500 million to expand its operations in Singapore, where the IC backend house is headquartered.
Thursday 31 January 2013
Scientech deepens development of 3D IC, wafer-level packaging equipment
Taiwan-based semiconductor equipment distributor Scientech has deepened its development of 3D IC packaging and wafer-level packaging equipment, expecting some of its equipment to...
Monday 19 March 2012
ChipMOS expects sales growth in 2012
Packaging and testing firm ChipMOS Technologies has forecast consolidated revenues for 2012 will increase 10%. The company revealed that net revenues on a US GAAP basis for 2011 grew...
Wednesday 14 March 2012
Aptos expanding 12-inch wafer level packaging business
Aptos Technology, which specializes in backend services for the production of NAND flash chips and devices such as microSD cards, announced March 13 that two of its subsidiaries will...
Wednesday 7 March 2012
STATS ChipPAC intros new 3D eWLB PoP solutions
STATS ChipPAC, a semiconductor test and advanced packaging service provider, has announced its next-generation three dimensional (3D) embedded wafer-level ball grid array (eWLB) package-on-package...
Friday 6 January 2012
STATS ChipPAC breaks ground for new factory
STATS ChipPAC on January 5 hold a groundbreaking ceremony for its new factory in Singapore, according to the chip test and packaging service provider. The new 197,000-square foot...
Monday 21 November 2011
Focus on small, cost-effective packages: Q&A with STATS ChipPAC CEO Tan Lay Koon
Despite uncertainties in the semiconductor industry outlook, packaging and testing firm STATS ChipPAC will continue investing in advanced IC packages for space-critical designs that...
Monday 14 November 2011
STATS ChipPAC to open new wafer-level packaging plant in Taiwan, says paper
STATS ChipPAC is scheduled to hold an inauguration ceremony for a 12-inch wafer bumping and wafer-level packaging plant in Hsinchu County, northern Taiwan, Thursday (November 17),...
Friday 1 July 2011
PTI developing advanced packaging technologies
Packaging and testing firm Powertech Technology (PTI) expects the development of new technologies including wafer-level packaging, 3D IC packaging and copper pillar bumping to bear...
Wednesday 29 June 2011
ASE aims at global market share of 25-30% in 2014
IC packaging/testing service provider Advanced Semiconductor Engineering (ASE) aims to hike its global market share from 17-18% in 2010 to 25-30% in 2014, COO Tien Wu said at the...
Tuesday 18 January 2011
STATS ChipPAC expands WLP offering with 12-inch manufacturing in Taiwan
STATS ChipPAC has announced the expansion of its wafer-level package (WLP) offering with new 300mm manufacturing capabilities in Taiwan. The 300mm WLP operation is located in Hsinchu...
Monday 4 October 2010
ASE to budget US$700 million in capex for 2011, says paper
IC packaging and testing house Advanced Semiconductor Engineering (ASE) plans to budget US$700 million in capex for 2011, flat on year, an unnamed company executive has been cited...
Wednesday 15 September 2010
STATS ChipPAC opens new plant for 300mm eWLB wafer manufacturing
STATS ChipPAC on September 15 celebrated the opening of a new manufacturing facility to process 300mm wafers using embedded wafer-level BGA (eWLB) technology. The Singapore-based...
Tuesday 14 September 2010
SPIL enters LED packaging market
Siliconware Precision Industries (SPIL) has entered the LED packaging business and started LED shipments through wirebonding packaging technology to three US-based clients. It is...
Monday 30 November 2009
Aptos invests in ACE to enhance wafer-level package offering
Aptos Technology, a 20%-held packaging and testing affiliate of Phison Electronics, has announced it recently acquired an 87% stake in wafer-level packaging (WLP) house Advanced Chip...
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