UCIe 3.0 doubles bandwidth, expands chiplet ecosystem — Intel's Das Sharma on AI and compatibility

The Universal Chiplet Interconnect Express (UCIe) standard has taken a decisive step forward with the release of version 3.0, delivering up to 64 GT/s throughput and doubling bandwidth density to meet the surging demands of AI, high-performance computing, and data-intensive workloads. Intel Senior Fellow Dr. Debendra Das Sharma, who chairs the UCIe Consortium, says the update cements the foundation for a fully open, backward-compatible chiplet ecosystem.

"These are open chiplet ecosystems," Das Sharma said in an interview. "If you design something for UCIe today, it will work with any future generations of UCIe. You don't have to change it."

That backward-compatibility promise, he explained, mirrors the enduring design philosophy of another key industry standard:

"If you bought a graphics card in 2004, that's PCI Express 5.0. It still works... Of course, it can't run at the latest speed, but it will still work. That's backward compatibility. We want to make that here."

Doubling speed for AI

The UCIe 3.0 spec raises the ceiling from 32 GT/s in the earlier planar connection to 48 GT/s and 64 GT/s, accommodating AI and other workloads that require enormous memory bandwidth.

"Your dimensions of the chip are not increasing, but you need more bandwidth," he said. "How do you do that? You just run those links faster… so my bandwidth density went up by about 2x."

The spec also builds on earlier milestones:

• UCIe 1.1 added automotive-focused features.

• UCIe 2.0 brought 3D chiplet support and package-level debug, manageability, and testability functions.

"By some projections, automotive is a significant chunk of the chiplets that are using UCIe," he noted.

Growing industry buy-in

The consortium, formed by Intel and other founding members in March 2022, has since grown to more than 140 companies. Nvidia recently joined as a board member — a step up from ordinary membership.

"They are on the board. They're not just any member, they're a board member," he said, adding that board members have "more responsibilities, expectations... It's a leadership position."

UCIe's on-package interconnect approach differentiates it from off-package solutions, enabling chiplets within a package to operate as a tightly integrated system.

"Inside each one of these boxes, it's like multiple chiplets connected," he explained. "That's the only way to connect chiplets—it's a must, just like on the board, you can't do the board without PCIe."

Efficiency and power management

Beyond speed, UCIe 3.0 introduces deeper power-saving modes for devices like laptops.

"When your laptop is in suspend mode, you're not using it, but when you open it, you want it to wake up instantly," he said. "In the deep sleep state, the key is you want to consume as little power as you can, because otherwise your battery will drain."

With 2x bandwidth, expanded manageability, and unwavering backward compatibility, UCIe 3.0 positions chiplets as a scalable, vendor-agnostic foundation for the next wave of computing. Under Das Sharma's stewardship, the consortium is rallying the industry around an open standard that could rapidly redefine how high-performance systems are built.

Source: UCIe Consortium, compiled by DIGITIMES, August 2025

Debendra Das Sharma, Intel Senior Fellow and the chair of the UCIe Consortium. Credit: Joseph Chen

Article edited by Jack Wu