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GUC announces GLink-3D die-on-die interface IP using TSMC N5 and N6 process for 3DFabric advanced packaging technology

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Global Unichip Corp (GUC), the advanced ASIC leader, announces GLink-3D die-on-die interface IP using TSMC's N5 and N6 processes and 3DFabric advanced packaging technology for AI, HPC, and networking applications.

AI/HPC/Networking memory demand is growing quickly and the SRAM to Logic ratio is also increasing. Logic gains higher density and performance when scaled to N5/N3 process nodes but SRAM scaling from N7 to N5/N3 is moderate. SRAM/Logic disintegration allows the implementation of separate SRAM and Logic at the most efficient process nodes. Layers of CPU and SRAM (Last Level Cache, packet buffers) dies can be assembled over and under interconnect/IO dies using TSMC 3DFabric packaging technology. Such expandable SRAM and modular computing applications are enabled by GUC GLink-3D high bandwidth, low latency, low power, and point-to-multipoint interface between 3D stacked dies. CPUs, SRAMs, Interconnects, and I/Os (SerDes, HBM, DDR) can be implemented in the most efficient process nodes. Different die combinations can be assembled to address different market segments. At boot time, assembled SRAM and CPU dies are identified, unique die IDs are distributed, available memory space and computing resources are defined and a point-to-multipoint GLink-3D interface to the stacked dies is enabled.

TSMC's 3DFabric SoIC platform technology allows much more efficient connectivity. GLink-3D achieved six times higher bandwidth/area density, six times lower latency and twice lower power consumption than best-in-class 2.5D interface GLink-2.0 (it was taped out in Dec 2020). Several 3D die stacks can be assembled using CoWoS and InFO_oS, interconnected using GLink-2.5D links and combined with HBM memories.

"GLink-3D is a new addition to a rich portfolio of best-in-class and silicon-proven HBM2E/3 PHY/Controller and GLink-2.5D IPs. CoWoS, InFO_oS, 3DIC expertise, package design, electrical and thermal simulations, DFT and production testing under one GUC roof provide our ASIC customers with quick design cycles, fast bring up and production ramp up." explains Dr. Ken Chen, president of GUC.

"3D die stacking technology will start a revolution in the way we design HPC, AI and Network Processors. Die-to-die interface is not limited any more to the die boundary, it can be located exactly where processors need to connect to SRAM and additional CPUs. 3DFabric and GLink-3D pave way to the processors of the future, combining huge and scalable processing power with vast, high bandwidth and low latency memory, when every component is implemented using the most efficient process node." said Igor Elkanovich, CTO of GUC.

GLink-3D key features:
*Supports TSMC-SoIC stacking of combination of N5 and N6 process nodes
*Point-to-multipoint interface allows the main die to interface with several stacked dies simultaneously
*Robust, full duplex 9Tbps traffic per mm2
*Speed: 5.0 Gbps per lane
*Extremely low end-to-end latency (< 2ns) with low power design (< 0.2pJ/bit)
*Single supply voltage 0.75V ± 10%

To learn more about GUC's HBM, GLink 2.5D/3D IP portfolio and InFO/CoWoS/SoIC total solution, please contact your GUC sales representative directly.

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