3D chip stacking tech competition intensifying

Julian Ho, Taipei; Rodney Chan, DIGITIMES Asia 0


TSMC has recently announced SoIC-P, microbump versions of its System on Integrated Chips (SoIC) solutions providing a cost-effective way for 3D chip stacking.

TSMC said SoIC-P complements its existing bumpless solutions for high-performance computing (HPC) applications, which are now known as SoIC-X.

According to industry sources from the semiconductor packaging and testing sector, SoIC-P is TSMC's answer to Intel's 3D Foveros.

The sources said TSMC's bumpless solutions are a little more advanced than the micro-bump tech of Intel's Foveros. But TSMC is now launching microbump versions, the SoIC-P,offering better cost competitiveness, the sources said.

Chiplets are expected to be the mainstream in the future. The processors that Intel is launching in 2023 and 2024 will embrace the chiplet concept of tile structure, the sources said, adding a balance can be maintained between cost and performance by combining CPUs made using advanced processes and I/O chips made using mature processes.

Intel has also unveiled its roadmap heading towards Foveros Omni and Foveros Direct.

In the CPU market, AMD is the major vendor embracing TSMC's 3D SoIC, the sources said, adding its premium AI chips employ TSMC's foundry services plus its backend SoIC+CoWoS services.

None of the above-mentioned companies commented on the report.