At the IEEE International Electron Device Meeting (IEDM) 2022, Intel unveiled research breakthroughs in 2D and 3D IC packaging technologies fueling its innovation pipeline for keeping its promises to put a trillion transistors on an integrated circuit (IC) by 2030.
Intel showcased advancements in 3D packaging technology with a new 10x improvement in density; new materials for 2D transistor scaling beyond RibbonFET, including super-thin material just 3 atoms thick; new possibilities in energy efficiency and memory for higher-performing computing; and advancements for quantum computing, according to a company press release.
At IEDM 2022, Intel's Components Research Group presented its innovations across three key areas, including new 3D hybrid bonding packaging technology to enable seamless integration of chiplets; super-thin, 2D materials to fit more transistors onto a single chip; and new possibilities in energy efficiency and memory for higher-performing computing.
Components Research Group researchers have identified new materials and processes that blur the line between packaging and silicon.
"We reveal critical next steps on the journey to extending Moore's Law to a trillion transistors on a package, including advanced packaging that can achieve an additional 10x interconnect density, leading to quasi-monolithic chips (QMC). Intel's materials innovations have also identified practical design choices that can meet the requirements of transistor scaling using novel material just 3 atoms thick, enabling the company to continue scaling beyond RibbonFET," said Intel's Component Research Group in the press release.
Intel is also building a viable path to 300 mm GaN-on-silicon wafers by making breakthroughs to demonstrate a 20 times gain over industry standard GaN and set an industry record figure-of-merit for high-performance power delivery.
In the area of quantum computing, Intel said it continues to introduce new concepts in physics with breakthroughs in delivering better ways to store quantum information by gathering a better understanding of various interface defects that could act as environmental disturbances affecting quantum data.
Tom's Hardware in an analysis wrote that QMC is a new hybrid bonding technique that features sub-3 micron pitches and results in a 10X increase in power efficiency and performance density over the research Intel submitted at last year's IEDM. That paper covered an approach with 10-micron pitches, which was already a 10X improvement. As this year's paper demonstrated, Intel has found a pathway to a 100X improvement in just a few years.
However, Tom's Hardware's deputy managing editor Paul Acorn pointed out that Intel's Components Research Group lays the initial groundwork for the company's future technologies, but not all of these initiatives will result in products that ship to market. "Those that do come to market would typically arrive in 5 to 10 years."