Chiplet interconnect startup Eliyan, backed by Intel and Micron, announced successful tape-out on TSMC's 5nm node

Misha Lu, DIGITIMES Asia, Taipei 0

Credit: AFP

Chiplet interconnect startup Eliyan Corporation, based in Califronia, has raised US$40 million Series A funding, backed by four investors including Intel Capital and Micron Ventures. The round was led by Tracker Capital Management. The startup was founded in 2021 by Ramin Fajadrad, Syrus Ziai and Patrick Soheili.

Farjadrad previosuly served as CTO at Marvell, leading its networking and automotive division. Ziai previosuly served as a Qualcomm engineering VP.

According to Eliyan, its technology - named NuLink - uses standard system-in-package (SIP) technology to connect chiplets, claiming to have achieved twice the bandwith and less than half of power consumption level compared to inerconnect methods based on advanced packaging methods. Targeting the markets of hyperscalers, data centers cloud computing, AI and graphics, the startup also said that standard chip packaging method saves time and cost when compared to more advanced packaging methods.

The startup stated that it has already successfully tapped out its interconnects using TSMC's 5nm process. Now armed with US$40 million, the Eliyan plans to ramp up testing and implementation, expecting its first product to hit the market in first-quarter 2023.

"Technology scaling using conventional system on chip (SoC) architectures is hitting the wall, requiring a new approach in how we integrate and manufacture silicon. Our extensive background in developing bleeding-edge technologies in this space led us to focus on a key challenge: interconnect improvements for system-in-package and chip-to-memory architectures as the path to deliver performance scaling," said Eliyan CEO and co-founder, Ramin Farjadrad, in the company's press release.

Notably, Eliyan pointed out that its NuLink technology is compatible with the Intel-led Universal Chiplet Interconnect Standard (UCIe), in addition to the High Bandwidth Memory (HBM) protocols. UCIe is growing in importance as Intel turns its attention to chiplet technology under CEO Pat Gelsinger's strategic overhaul.

In a Linkedin post published on November 4, Gelsinger specifically names chiplet standard as one of the four components of the 'Systems Foundry' Intel is seeking to create, alongside Moore's Law, packaging and software. The launch of UCIe Consortium, together with industry leaders like TSMC, AMD, ASE and Samsung, pointed to Intel's intention to create a single industry standard for chiplets.