TSMC debuts A16 technology at 2024 North America Technology Symposium

Jessie Shen, DIGITIMES Asia, Taipei 0


At the 2024 North America Technology Symposium, TSMC demonstrated its latest semiconductor process, advanced packaging, and 3D IC technologies, which will drive the next wave of AI developments with silicon leadership.

Among these is the TSMC A16 technology, which combines leading nanosheet transistors with an innovative backside power rail solution for 2026 production, yielding dramatically higher logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution that brings revolutionary performance to the wafer level while addressing future AI requirements for hyperscaler data centers.


With TSMC's industry-leading N3E technology now in production and N2 scheduled for production in the second half of 2025, the company introduced A16, the next technology on its roadmap.

TSMC A16 will combine TSMC's Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC's N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15-20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.


TSMC also announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025. N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

NanoFlex innovation for nanosheet transistors

TSMC's upcoming N2 technology will come with TSMC NanoFlex, the company's next breakthrough in design-technology co-optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers can optimize the combination of short and tall cells within the same design block, tailoring their designs to achieve the best power, performance, and space tradeoffs for their application.

CoWoS, SoIC, and SoW

TSMC's CoWoS has been a key enabler for the AI revolution by allowing customers to pack more processor cores and High Bandwidth Memory (HBM) stacks side by side on one interposer. At the same time, TSMC's SoIC has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate System-in-Package (SiP) integration.

With system-on-wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude. TSMC's first SoW offering, a logic-only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM, and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon photonics integration

TSMC is developing Compact Universal Photonic Engine (COUPE) technology to handle the exponential increase in data transmission that will accompany the AI boom. COUPE employs SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, resulting in lower impedance at the die-to-die interface and improved energy efficiency than traditional stacking methods. TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as Co-Packaged Optics (CPO) in 2026, which will bring optical connections directly into the package.

Automotive advanced packaging

After releasing the N3AE "Auto Early" process in 2023, TSMC continues to address its automotive customers' requests for increased computing power that meets highway safety and quality standards by combining advanced silicon with advanced packaging. TSMC is developing InFO-oS and CoWoS-R solutions for applications such as Advanced Driver Assistance Systems (ADAS), vehicle control, and vehicle central computers, to achieve AEC-Q100 Grade 2 qualification by the fourth quarter of 2025.