Cadence Design Systems has announced the availability of a Cadence Rapid Adoption Kit (RAK) for the new ARM Cortex-R52 CPU, which targets complex embedded designs for safety applications...

Micron Technology has announced its newest embedded SLC NAND flash optimized for the next generation of Internet of Things (IoT) and automotive applications. Available with differing...

Cadence Design Systems has announced that its implementation and signoff tools have been certified on the Intel third-generation 10nm tri-gate process for customers of Intel Custom...

Cadence Design Systems has announced the availability of a Rapid Adoption Kit (RAK) based on the ARM internal flow used for the design of the ARM Cortex-A73 central processing unit...

Cypress Semiconductor has selected the full Cadence RTL-to-signoff digital design flow and complete Spectre circuit simulation platform for all of its 40nm automotive chip designs,...

Toshiba has adopted the Cadence Innovus implementation system for its memory controller's production design project, according to the EDA company. The tool enabled Toshiba...

Cadence Design Systems has announced that the company's Virtuoso layout-dependent effects (LDE) analyzer has been qualified by United Microelectronics (UMC) to support the foundry's...

Cadence Design Systems has announced that its complete suite of digital and signoff tools has achieved certification for Samsung Foundry's process design kit (PDK) and foundation...

Cadence Design Systems has announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET...

Cadence Design Systems has announced the availability of foundry-proven IC packaging design and analysis solutions for advanced fan-out wafer-level chip scale packaging (WLCSP) and...

Cadence Design Systems has announced the delivery of the new Virtuoso advanced-node platform that is enabled for all 10nm FinFET designs. This next-generation custom design platform...

Cadence Design Systems has announced that its digital and signoff tools are now enabled for the current version of the Globalfoundries 22FDX platform reference flow. Globalfoundries...

Cadence Design Systems has announced the Cadence Memory Model for the LPDDR5 standard. This new verification IP (VIP) product enables engineers to verify that system-on-chip (SoC)...

Nano-electronics research center imec and Cadence Design Systems have announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as...

Cadence Design Systems has announced that its Allegro system-in-package (SiP) and physical verification system (PVS) implementation technologies have been enabled for TSMC's integrated...