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Monday 24 December 2018
2018 review and 2019 outlook: How Taiwan ICT industry can regain ground
The US-China trade war, a key threat to the global economy in 2018, will continue to play a pivotal role in 2019. But what does it mean to the world's biggest manufacturer and market,...
Thursday 16 August 2018
Cadence to open subsidiary in Nanjing
EDA vendor Cadence Design Systems is scheduled to start operating a new subsidiary in Nanjing, China in September, according to industry sources.
Wednesday 9 May 2018
Cadence DDR5 IP test chip runs with Micron prototype DRAM
Cadence has disclosed a test chip containing next-generation DDR5 memory interface IP, which operates with Micron Technology's prototype DRAM chips. The test chip was fabricated in...
Monday 7 May 2018
Cadence Innovus implementation tool speeds development of new Realtek DTV SoC solution
Cadence Design Systems has announced that Realtek Semiconductor used the Cadence Innovus implementation system for its 28nm Digital TV (DTV) system-on-chip (SoC) production tapeout...
Friday 2 February 2018
ASE, Cadence deliver SiP EDA solution
Advanced Semiconductor Engineering (ASE) and Cadence Design Systems have collaborated to release a system-in-package (SiP) EDA solution that addresses the challenges of designing...
Wednesday 15 November 2017
HiSilicon selects Cadence Tensilica Vision P6 DSP for Kirin 970
Cadence Design Systems has announced that HiSilicon, a global fabless semiconductor and IC design company, has selected the Cadence Tensilica Vision P6 DSP for its 10nm Kirin 970...
Tuesday 12 September 2017
Xilinx, ARM, Cadence and TSMC collaborating on CCIX test chip
Xilinx, ARM, Cadence Design Systems and TSMC have announced a collaboration to build the first CCIX (cache coherent interconnect for accelerators) test chip in TSMC 7nm FinFET process...
Thursday 20 April 2017
ASML secures pull-in of EUV equipment orders
ASML has landed a pull-in of EUV lithography equipment orders with its backlog reaching 21 units, according to the company.
Wednesday 26 October 2016
Cadence IP tools certified on Samsung 10nm process technology
Cadence Design Systems has announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics' Process Design Kit (PDK) and Foundation Library...
Monday 24 October 2016
Fujitsu adopts Cadence Palladium Z1 enterprise emulation platform
Cadence Design Systems, has announced that Fujitsu has adopted the Cadence Palladium Z1 enterprise emulation platform for the development of the ARMv8-based Post-K computer. The Post-K...
Monday 26 September 2016
Cadence, TSMC advance 7nm FinFET designs for mobile and HPC platforms
Cadence Design Systems has announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platf...
Friday 23 September 2016
Cadence delivers integrated system design solution for TSMC InFO packaging technology
Cadence Design Systems has announced the immediate availability of an integrated system design solution for TSMC's advanced wafer-level integrated fan-out (InFO) packaging technology,...
Wednesday 21 September 2016
Cadence delivers tools for implementation and signoff of new ARM Cortex-R52 CPU
Cadence Design Systems has announced the availability of a Cadence Rapid Adoption Kit (RAK) for the new ARM Cortex-R52 CPU, which targets complex embedded designs for safety applications...
Friday 15 July 2016
Micron intros SLC NAND flash for IoT and automotive
Micron Technology has announced its newest embedded SLC NAND flash optimized for the next generation of Internet of Things (IoT) and automotive applications. Available with differing...
Wednesday 13 July 2016
Intel certifies Cadence implementation and signoff tools for 10nm tri-gate process
Cadence Design Systems has announced that its implementation and signoff tools have been certified on the Intel third-generation 10nm tri-gate process for customers of Intel Custom...