Japan is eyeing heterogeneous integration on way to mass-produce 2nm chips

Chiang, Jen-Chieh, Taipei; Jingyue Hsiao, DIGITIMES Asia 0

Credit: Intel

As Japan is developing the technology for mass-producing 2nm chips, they are not only trying to increase the transistor density on a single die but also to combine multiple dies with heterogeneous integration.

Rapidus has focused on heterogeneous integration since its establishment in August 2022, trying to combine multiple dies in a single system by 2.5D and 3D integration. According to its website, the Japan-based semiconductor manufacturer plans to collaborate with Western counterparts to develop the next-generation 3D LSI and mass-produce sub-2nm chips with leading-edge LSI technology.

The Japanese Ministry of Economy, Trade, and Industry (METI) revamped The Strategy for Semiconductors and the Digital Industry in June, identifying 2.5D and 3D packaging and silicon bridge as the technologies to make a breakthrough by the late 2020s. METI aims to launch the Leading-edge Semiconductor Technology Center (LSTC) to lead the efforts, collaborating with Rapidus and overseas research institutions and manufacturers to jointly develop these technologies and to apply the advanced packaging technology to sub-2nm chips in the latter half of the 2020s.

Nikkei Electronics reported that Japan-based companies formed JOINT2 (Jisso Open Innovation Network of Tops 2). The alliance, supported by METI with members including Renosac, Ajinomoto Fine-Techno, Uyemura, Ebara, Shinko Electric Industries, DNP, Disco, TOK, Namics, Panasonic Smart Factory Solutions, MEC, Yamaha Robitcs Holdings, and Orc Manufacturing, will collaborate with Rapius and LSTC for advanced packaging.

Despite the absence of prominent wafer fabs and OSAT companies, Japan is looking to capitalize on its advantages in materials and equipment to make a foray into semiconductor manufacturing. However, developing chiplets technologies in Japan may not be deemed necessary from the perspective of the US, which is building its own semiconductor ecosystem. Furthermore, the UCIe alliance, which aims to coordinate interconnection standards for chiplets technology, does not include Japanese companies as contributor members. Whether these issues will affect the development of Japanese companies in heterogeneous integration remains to be seen.