Synopsys certifies AI design flows on Samsung 2nm

Jessie Shen, DIGITIMES Asia, Taipei 0


Synopsys has announced that its AI-driven digital design and analog design flows have achieved certification on Samsung Foundry's SF2 process with multiple test chip tape-outs.

The reference flows, driven by the full-stack EDA suite, enhance PPA, boost productivity, and accelerate analog design migration for Samsung Foundry's latest GAA process technologies. The Samsung SF2 process was optimized utilizing Synopsys' AI-driven Design Technology Co-Optimization (DTCO) solution, which resulted in significantly improved process Performance, Power, and Area (PPA) compared to non-AI optimization. Building on this success, the same co-optimization approaches will be used for Samsung's more advanced SF1.4 process.

Collaboration on AI-driven EDA flows

Synopsys and Samsung are closely collaborating on AI-driven flows, including Synopsys for design productivity and PPA optimization, and Synopsys for faster analog design migration. This collaboration has resulted in a new analog design migration reference flow using Synopsys for Samsung's FinFET to GAA processes, enabling designers to efficiently migrate Samsung 8nm analog IPs to the SF2 process, adding to Synopsys' established flows on Samsung's 14nm to 8nm/SF5 processes.

Synopsys' continued innovation helps mutual customers benefit from new design techniques including backside routing, local layout effect-aware methodology, and nanosheet cell design, to help customers meet their design goals for power, performance, and area on Samsung SF2 process family. In addition, integrating backside routing and the super-cell approach using Synopsys' digital implementation and signoff tools enables designers to increase transistor performance efficiency and density, optimize power consumption, and reduce area by up to 20% for Samsung's SF2Z process technology compared to chips without backside routing capabilities.

Accelerate SoC and multi-die designs

Synopsys IP for Samsung standard and automotive processes from SF2 to SF14LPU delivers a competitive edge for chipmakers looking to reduce integration risk and accelerate time to silicon success for automotive, mobile, High-Performance Computing (HPC), and multi-die designs. The industry's broadest portfolio of standards-compliant, silicon-proven interface IP for advanced Samsung processes, including PCIe 6.0/5.0/4.0, DDR5, LPDDR5X/5/4X, MIPI M-PHY G5, eUSB2, USB 3.2/3.1, and DisplayPort enables wide interoperability for commonly used protocols.

To accelerate the integration of chiplets in multi-die packages, Synopsys UCIe IP has taped out in SF2 and SF4x, and achieved silicon success in SF5A process technologies, to deliver robust die-to-die connectivity with low power and low latency. Synopsys Foundation IP, including embedded memories, logic libraries, and GPIOs, is also proven in silicon to deliver leading power, performance, and area in a range of Samsung process technologies.

Mutual customers can accelerate the development of multi-die designs using Synopsys 3DIC Compiler, a unified exploration-to-signoff platform for 2.5D and 3D heterogeneous integration and advanced packaging. Qualified for Samsung Foundry's SF2 process, Synopsys 3DIC Compiler supports Samsung's advanced silicon processes, packaging technologies, and 3DCODE standards. Synopsys is an active member of the Samsung Foundries' MDI Alliance, helping mutual customers achieve a successful transition to 2.5D and 3D advanced packaging designs.

"This latest collaboration milestone with Synopsys on AI-driven EDA flows and broad IP portfolio development is a testament to our ongoing efforts to address the industry's growing demand for high-performance computing with significant PPA gains," said Sangyun Kim, VP and head of Samsung's foundry design technology team, in Synopsys' statement. "Working together we validated our PPA results using Synopsys' certified digital flow, achieving 12% higher performance, 25% reduction in power, and 5% area reduction compared to the base design."