China looks to AI-generated chip design as US tightens EDA chokehold

Misha Lu, DIGITIMES Asia, Taipei 0

Credit: China Academy of Science

Scientists from the Institute of Computing Technology under Chinese Academy of Sciences have recently published a research paper showcasing capability to use AI in automating chip design. Titled "Pushing the Limits of Machine Design: Automated CPU Design with AI", the research claims that a 32-bit RISC-V CPU design was automatically generated within 5 hours, and that the CPU, with a clock rate up to 300MHz, already entered tape-out in December 2021 on 65nm process. In addition, the research claimed that the CPU was tested successfully on the Linux operating system and performed "comparably against the human-designed Intel 80486SX CPU."

Though modern commercial electronic design automation (EDA) tools such as logic synthesis or high-level synthesis tools are available to accelerate the CPU design, all these tools require hand-crafted formal program code as the input," the research paper explained." In other words, engineers must use formal programming languages to implement the circuit logic of a CPU based on design specification, before various EDA tools can be used to facilitate functional validation and performance/power optimization of the circuit logic.

The highly complex process typically iterates for months or years, "where the key bottleneck is the manual implementation of the input circuit logic in terms of formal program code," indicated the paper. What the research group aimed for was automating the CPU design without human programming. It was done by using partial input output examples to replace human-written programs as the inputs, as such examples were directly accessible from a large number of legacy test cases.

Therefore, according to the research, "The problem of automated CPU design can be formulated as generating the circuit logic in the form of a Boolean function satisfying the input-output specification." Using the approach, the report claimed to successfully generate "a large-scale Boolean function with almost 100% validation accuracy (e.g., > 99.99999999999% as Intel) from only external input-output examples". Notably, the paper claimed that the adopted approach could discover not only the general von Neumann architecture, but also fine-grain architecture optimization from scratch,

Despite the claimed success, this only marks the first step. If the design complexity was increased, with a more complex CPU and some other IP blocks, tougher performance targets have to be met to evaluate how good the AI flow is, according to Woz Ahmed, Managing Director of Chilli Ventures and former Chief Strategy Officer of Imagination Technologies. "Setting aggressive design constraints with a new process and integrating complex IP is the real test, to see if automation will match experienced engineers in power, performance and area (PPA), testability and manufacturability," Ahmed observed.

"Given the US chokehold on EDA tools, China's best hope in indigenous EDA is to leverage its broad AI capabilities," Ahmed further noted, "they need to be getting hold of lots of relevant training data."