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NEWS TAGGED 3D-STACKING
Tuesday 6 October 2009
Suss MicroTec teams up with ITRI for development in 3D integration
Suss MicroTec, a supplier of process and test solutions for the semiconductor industry and related markets, has announced that it is engaging with the Industrial Technology Research...
Tuesday 6 October 2009
IMEC sets major step towards 3D integration of DRAM on logic
Leuven, Belgium - September 30, 2009 - IMEC and its 3D integration partners have taped-out Etna, a new 3D chip integrating a commercial DRAM chip on top of a logic IC. The new 3D...
Friday 2 October 2009
3D IC packaging to be mature within 3 years, says ASE chief officer
Advanced 3D packaging has been adopted in image sensor ICs used in camera lens modules which recently entered volume production, and will be applied into CPUs, baseband ICs, and handset...
Tuesday 25 August 2009
PTI purchase of Spansion backend facility in China to target non-memory products, say sources
Powertech Technology (PTI) aims to turn the China plant it is buying from Spansion into its major production base for non-memory packaging and testing, covering logic ICs, SiP (system...
Tuesday 7 April 2009
TSV development picking up momentum
Unlike conventional SoC or SiP solutions that integrate ICs on a two-dimensional (2D) surface, using through silicon via (TSV) technology in a package that stacks ICs in a three-dimensional...
Wednesday 15 October 2008
Taiwan to mass produce TSV by 2010
Taiwan's Semiconductor Industry Promotion Office under the Ministry of Economic Affairs (MOEA) and Industrial Technology Research Institute (ITRI) recently gathered experts to discuss...
Thursday 24 July 2008
3D-stacking IC consortium established in Taiwan
Driven by growing demand for strong IC design integration, Taiwan's Industrial Technology Research Institute (ITRI) recently established a consortium for advanced stacked-system technology...