Improved testing is important, but cost is key. Healy cited Qualcomm as finding no problems in 61% of field returns; he attributed this to insufficient testing.
Because of current organization, DFT may be cut to save cost and speed time to market, but this may be a false saving. Small increases in design time can improve time to market and reduce cost of tests. With wafer-level testing at full speed (with BIST), yield at final test improves. This also means less testers as test times are faster.
DFT is a value play, not a cost play.
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- Musk says chip capacity will decide winner of AI race (Mar 21) - EE Times
- Google taps MediaTek for cheaper AI chips (Mar 17) - The Information
- European project gets $260 million for HPC chip sovereignty (Mar 6) - EE Times
- The trouble with MAGA's chipmaking dreams (Mar 3) - Economist
- Automotive chips: Gloom and doom or boom by 2030? (Feb 14) - EE Times
- Deepseek is more Wall Street than Silicon Valley (Feb 3) - Culpium, by Tim Culpan
- Tech CEOs try to reassure Wall Street after DeepSeek shock (Jan 30) - Wall Street Journal
- TSMC to make chips for cryptominer Bitdeer at new US fab (Jan 17) - Culpium, by Tim Culpan
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