DIGITIMES observes that since ChatGPT sparked the generative AI (GenAI) wave in 2022, global demand for AI computing power has risen sharply, fueling massive demand for AI chips. However, the significant power consumption and insufficient data-transmission efficiency caused by heavy computing workloads have become major bottlenecks in AI chip development.
This has pushed the industry to seek high-performance, low-power solutions actively. Among them, co-packaged optics (CPO) technology has emerged as a key direction for AI chip packaging development because it can shorten electrical transmission distances, reduce power consumption, and increase bandwidth.
Currently, TSMC, ASE Technology Holding, and FOCI Fiber Optic Communications are core players in Taiwan’s CPO technology development. TSMC plans to combine its COUPE optical engine with the CoWoS platform to advance system integration and standardization; ASE aims to strike a balance between performance and yield through fan-out stacked packaging and 3D packaging solutions; and FOCI focuses on fiber array alignment and packaging stability to improve the yield and reliability of optical modules.
AI chips must get faster to bypass power and data bottlenecks
Chart 1: Signal loss in high-frequency data transmission paths of AI chips
Optoelectronic integration offers effective solutions for AI chips
Chart 2: Development of optoelectronic integration and advanced packaging techs
Chart 4: Diagram of package reflow soldering temperature changes
Chart 5: TSMC's compact optical engine development framework
ASE offers two packaging solutions, with data rates hitting 200 Gbps
Chart 7: Overview of FOCI's key solution features and patent portfolio
Chart 8: TSMC, ASE, FOCI investment for addressing CPO commercialization challenges
