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Imagination popular Codescape tools now provide MIPS CPU support and extended Linux/RTOS capabilities
Press release

Imagination Technologies announced that the latest version of its popular Codescape debugger now supports the full range of MIPS CPUs, offers new Linux and RTOS awareness features, and provides heterogeneous debug of SoCs using one or more of Imagination's portfolio of MIPS and Ensigma processors. With Codescape 8.0, Imagination's customers and developers have a complete, proven and powerful debug solution that goes beyond the CPU.

Codescape is used by Imagination and its licensees for fast, easy debugging across a wide range of Imagination's programmable IP, including MIPS CPUs and Ensigma RPUs (radio processors) with PowerVR GPU (graphics processor) support coming in 2014. With Codescape, developers can simultaneously examine the code of each of these processors, as well as the interactions between them, accelerating product development and enabling faster time to market. The Codescape debugger provides comprehensive debug across the whole SoC, supporting multiple operating systems, architectures and technologies, including the MIPS instruction set architecture (ISA), MIPS SIMD architecture (MSA), the Ensigma Modulation and Coding Processor (MCP) ISA and hardware multi-threading.

Says Tony King-Smith, EVP marketing, Imagination: "Imagination has been investing in our innovative Codescape heterogeneous debugging technology for more than a decade in support of our broad and expanding portfolio of processor IP. Our proven Codescape tools are an integral and strategic part of our comprehensive software toolchain, with powerful features and advanced functionality that work across our IP cores. We believe that Codescape is the only truly heterogeneous debugging technology, giving our customers a distinct competitive edge."

Codescape is a fast and fully-featured graphical debugger that includes the following features:
*Multi-core, multi-thread and multi-OS task support
*Ability to debug MIPS CPUs, Ensigma RPUs and other Imagination IP on the same SoC in a single view
*Bare metal, Linux and RTOS aware debug
*Support for Windows, Linux and Mac OS hosts including 64-bit
*Powerful graphical scripting for greater control and visualization of target data
*Supported by a range of high-speed JTAG and trace probes
*Supports connection to MIPS Instruction Accurate Simulator (IASim) and QEMU (Emulator)

Codescape can be used both with the powerful Codescape GUI and as a plugin with Eclipse. With built-in graphical scripting for data visualisation, virtual prototyping and debugger extendibility, Codescape is compatible with a range of emulators, FPGA systems and final silicon.

Future additions will include support for 64-bit MIPS cores, MIPS SIMD architecture and other new micro-architectural and ISA features.


A range of Codescape 8.0 debugger products, targeting different feature sets and capabilities, is available now. Contact for more information.

About Codescape

The Codescape development environment delivers new levels of development tool integration, tackling all aspects of high-performance, heterogeneous SoC platform development, and includes support for an ever increasing number of Imagination's programmable IP cores.

Codescape is an end-to-end solution, supporting development needs from IP evaluation through to product delivery and customer support. The one-stop solution eases the development cycle and helps Imagination's customers deliver the quality of finished product that their customers expect in the fastest possible timeframe.

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