Cardiovascular disease – diseases of the heart or the blood vessels that move blood to and from the heart – were responsible for an estimated 32 per cent of deaths worldwide, or just under 20 million deaths, in 2022, according to the World Health Organisation. Their takeaway? "It is important to detect cardiovascular disease as early as possible so that management with counselling and medicines can begin."Electrocardiograms (ECGs), a series of peaks that represent each heartbeat, depict the heart's electrical activity over time. An abnormal ECG (compared to one's baseline) can be indicative of arrhythmias, the medical term for irregular heartbeats that, in most cases, are not serious but can sometimes lead to strokes, heart attacks, and death. Patients can wear Holter monitors to continuously measure their ECG, but that entails placing a large number of electrodes (between three and eight, and up to twelve for greatest accuracy) on the skin, and wearing a piece of recording equipment around the neck or waist. Not only can this be inconvenient, but up to half of all patients reported some sort of skin irritation due to the electrodes.Smartwatches can also be used to measure an ECG, but only when both hands touch the device – in other words, they cannot be used for passive, continuous heart monitoring. That's where integrated circuits can help. Students at the Hanoi University of Science and Technology (HUST) are working on an integrated circuit that can continuously monitor the heart's electrical activity through the ear. Such devices are already commonplace, with many people wearing hearing aids or smart hearables for at least some of the day. There are three physical connection points – both ears and one earlobe – the minimum required to measure an ECG.The ECG collected between the ears is useful only insofar as it can then reconstruct what lead-1 ECG, which is the electrical activity as would be measured by electrodes placed on the right and left arms. The lead-1 ECG is also a standard ECG measurement that is used for diagnosis and monitoring arrhythmias. There are generally similarities between the ear ECG and the lead-1 ECG – in particular, the peaks (representing the heartbeats) appear at the same location – but they are clearer in the lead-1 ECG than in the ear ECG.So while the algorithm on the chip must be able to recover the shape of the original lead-1 ECG with as little noise as possible, it should not smooth over any possible signs of abnormality – in other words, it needs to be sensitive enough to detect arrhythmias when they are present.The system is relatively unobtrusive and runs on low power, but using the ear also presents disadvantages. The signal-to-noise ratio is low. In fact, simply shaking one's head or talking will introduce noise into the measurements. Furthermore, special data privacy concerns when collecting biological signals – each user has a unique ‘heartprint’ and some users might be particularly wary of sending such data to another machine – make it imperative that any analysis is done on the chip itself.The user himself can measure his own lead-1 ECG using his two fingers (as proxies for the right and left arms), and measure his ear ECG with the devices touching his ear. All of this is done with electrodes attached to a sensor (with a built-in analog-digital convertor, or ADG) developed by Texas Instruments. Two datasets were created to train the AI calibration algorithm for the conversion between the ear and lead-1 ECGs. Firstly, the team collected its own dataset, measuring the ECGs for 45 patients for 10 minutes each. A synthetic public dataset was also created by modifying an existing large, open dataset of ECGs, the PTB-XL. This dataset doesn't include ear ECGs, so the team added noise to existing lead-1 measurements (in an attempt to emulate the ear ECG) and tried to recover the original, non-noisy lead-1 ECG. The team, which calls itself EDABK Brain, was able to bring the algorithm's latency, or delay time between receiving the ear ECG and producing the lead-1 ECG, down to below 50 milliseconds. Such short times obviate the need to store data from the ear-ECG, for instance. At the same time, they maximised the utilisation of the processing element, meaning that they worked hard to make sure the chip was effective.After prototyping a field-programmable gate array (FPGA) with their IC design, the team trained it on the self-collected dataset. On the two most important metrics, the signal-to-noise ratio and the correlation with the true lead-1 ECG, EDABK Brain slightly outperformed state-of-the-art algorithms. It was edged out by another algorithm – but the HUST model used fewer than a quarter as many parameters as that algorithm did.For another comparison, EDABK Brain's circuit used less power and was more energy efficient than BioGAP, a leading biosensing platform that can measure ECGs as well as other electrical signals in the body. However, BioGAP's circuit has a lower latency time and a high throughput (measured in operations per second).The team behind this chip design, the EDABK Brain Team (the EDA stands for electronic design automation, and the BK stands for Bách khoa, which is in the Vietnamese name of their university,  consists of Phuong Linh Nguyen, a student who graduated from their university last year and is now studying for a master's degree at Télécom Paris (one of the most prestigious French grandes écoles and part of the Polytechnic Institute of Paris), and who spoke to DIGITIMES; and her two former classmates, Thanh Dat Do and Duc Tu Nguyen, both of whom are in their final year in the School of Electronics and Electrical Engineering at HUST; and their supervisor, Duc Minh Nguyen. Having the chance to participate in the Best AI Awards motivates Nguyen and her teammates. Being just students at the start of their scientific career, they were curious to know what industry professionals thought of their idea – does it have potential? Winning the bronze medal is confirmation that it indeed does have potential.Nguyen said that it was also a relatively rare opportunity for them to communicate their ideas in a non-academic setting. Their university was able to send three teams to the finals, which also entailed a trip to Taiwan and interactions with state-of-the-art AI and IC researchers.They will now focus on writing a paper – after all, they come from academia – and preparing patent applications. On the technical side, they want to reduce the number of bits in their resolution – in other words, see whether they can convert the analog signal to a digital one with a fewer number of bits and less accuracy – to reduce complexity and thereby power consumption. The team will also experiment with other electrodes.The Best AI Awards celebrate global excellence in artificial intelligence and IC design, welcoming submissions from innovative companies and brilliant student teams. Following the success of the 2026 edition—advised by the MOEA, organized by DoIT, and executed by TCA—the prestigious competition is officially transitioning into an annual tradition.Offering substantial grand prizes and unmatched industry exposure, the countdown to Best AI Awards 2027 has already begun. Details on the next submission cycle, prize tiers, and eligibility rules will be released soon. Connect with us on LinkedIn for the latest official updates and application alerts.

The Best AI awards were given out in two categories: artificial intelligence (AI) applications and integrated circuit (IC) design. AIYO was entered in the IC design category, but their concept – AI-powered acceleration of IC design – really straddles the two categories.Chip design is a long, arduous process. Today's chips contain billions of transistors, and designers not only have to design them to do what they want them to do, but have to ensure that the design satisfies a large number of rules and can actually be physically produced in a foundry. Since 2010, the number of transistors and gates has increased by nearly a hundredfold, but engineering productivity (as measured by the number of gates that a chip designer can design in a day) has increased by only about three times. This 29-times gap is set to widen even further over the next few years. In other words, it takes chip engineers more time than ever before to do their job.The problem lies not solely in the number of components on a chip but in the complexity in how they interact. The demand for custom silicon – ICs specially designed and optimised for specific applications or customers – and the sheer number of use cases now being designed for is growing, but it is getting harder and harder to find the engineering talent for custom silicon. Specialised silicon requires specialised talent.Tier-one design houses, like NVIDIA or MediaTek, can still find talent, but it's a different story for tier-two companies. Chip design is increasingly a bottleneck for technology companies to implement their AI-powered (and non-AI-powered) solutions.AIYO thinks that AI can help with that. It aims to reduce the gap between tier one and tier two companies, without completely replacing human design and the need for engineers. Engineers use natural language to provide their design specifications, including the constraints and requirements that the chip must satisfy. AIYO's AI agent then generates Verilog, which is a piece of code that describes the design of digital circuits.This Verilog must satisfy the specifications that the user set out. AIYO's agent can also optimise it along various metrics, such as for a lower power consumption, a higher performance (in other words, how fast the chip operates, as measured by its clock speed or data throughput), or a smaller area (PPA) are the most commonly invoked. Different chips prioritise these three factors (collectively known as PPA) differently, but AIYO can trade off, for example, a lower performance for a lower area and less power consumption.AIYO's agent then performs a closed-loop verification of the design to ensure that it is feasible. The agent reviews the error logs and iterates the design until the design passes all tests. Then – at least theoretically – the design is ready for tape-out, or actual production of the circuit at the foundry. Tape-out is an expensive process, costing in the millions of dollars, so it is essential that the finalised design performs as expected.AIYO uses RISC-V, an open-source instruction set architecture (ISAs) that has grown exponentially in popularity since its introduction in 2014; it has already been used in more than 20 billion cores. This avoids the need to pay a licensing fee to the more common (but not open-source) ISAs in use today, such as ARM or x86.The performance of IC-design agents can be measured using a standard set of test problems. Can the agent solve the problems (i.e., design a suitable IC) on the first pass? And can it solve a different set of IC design problems eventually, after however many iterations? AIYO performs at the head of the pack in both models, a little bit ahead of NVIDIA's VerilogCoder agent and far ahead of ChatGPT, DeepSeek, and Claude. One to two engineers are now required to design a chip, where three to five would have been needed before. Furthermore, it now takes these one or two engineers two months to design a chip (and they can test multiple designs simultaneously), whilst those three to five engineers in a traditional design house would have needed six months. This is an improvement in efficiency of roughly an order of magnitude.AIYO is still a work in progress, and humans are needed to check for any mistakes the engine might make – human engineers' jobs are safe, at least for now. But AIYO does makes it possible to compress the iteration cycle and for even tier-two chip design companies to realise their designs with limited human resources.One of AIYO's most pressing next steps is expanding its customer base – not only for commercial reasons, but also because this will expand their training data and thus improve their AI engine. AIYO currently has one customer who needs help designing custom FPGA (field-programmable gate array) integrated circuits. AI is, by default, a generalist, and its large language models can fail when faced with very specific use cases that it has yet to see. Helping this customer with its specific use cases can help the AI engine gain specialist skills, and the more customers that AIYO can obtain, the more versatile the tool will be.To this end, the team is expanding the set of design problems. A large set of open-source IC design problems already exists, but AIYO is also working on building their own set of synthetic design problems.The money from the Best AI Awards is great, says Ballard, but realistically, it is not even enough for one year's access to a top EDA (electronic design automation) tool – training AI models is expensive. He says that the biggest benefit from the awards is the people it has allowed them to meet, and in particular, the conversations they've been able to have. "They'll ask, 'Did you consider X, Y, and Z?' Sometimes yes, we have, but sometimes, we have an action item for the future."This also gives them an opportunity to enter talks with various venture capital investors and potential Taiwanese partners. AIYO is currently working with funding provided by the co-founders themselves, but they're hoping to find a Taiwanese venture capital investor in the next few months.Tang-Hung Po and Austin Ballard have been working on AIYO for only roughly a year. Po, originally from Taiwan and now based back in the country, obtained his master's in electrical engineering and computer science from the University of Michigan; he is the company's primary engineering lead. He brings more than 20 years of experience in SoCs (systems on a chip) and ASICs (application-specific integrated circuits) to AIYO, and was previously a director and a chief technical officer at other companies.Ballard, an American based in Seattle but with a Taiwanese mother, brings his experience scaling operations at Meta, Amazon and TikTok to now handle anything at AIYO not related to engineering,  The time difference allows them to collaborate during Ballard's evenings and Po's mornings, and their almost diametrically opposite locations, along with their different skill sets, facilitates engagement with all sorts of partners on both sides of the world. (As a side benefit, Ballard now has a business reason to visit Taiwan!)The Best AI Awards celebrate global excellence in artificial intelligence and IC design, welcoming submissions from innovative companies and brilliant student teams. Following the success of the 2026 edition—advised by the MOEA, organized by DoIT, and executed by TCA—the prestigious competition is officially transitioning into an annual tradition.Offering substantial grand prizes and unmatched industry exposure, the countdown to Best AI Awards 2027 has already begun. Details on the next submission cycle, prize tiers, and eligibility rules will be released soon. Connect with us on LinkedIn for the latest official updates and application alerts.

The Ministry of Economic Affairs officialized the successful conclusion of the second annual Best AI Awards, held at the Taipei Nangang Exhibition Center Hall 2. This year's event witnessed an extraordinary surge in international engagement, drawing 1,487 competing teams from 36 countries across the globe, which represents a near two-fold growth in foreign participation compared to the inaugural edition. Out of 253 finalist teams, 100 awards were presented to recognize exceptional breakthroughs in artificial intelligence technology and integration.Leading Innovators Secure Top Honors Across Key Industry VerticalsThe competition highlighted highly competitive solutions spanning healthcare, information and communications technology, manufacturing, and education. Eight prestigious gold medals were awarded to outstanding organizations and academic institutions, including Delta Electronics, Kneron, BrainNavi Biotechnology, ZenTech, National Cheng Kung University, and National Formosa University, alongside pioneering international teams from Thailand and Poland. These entries showcased the practical implementation of artificial intelligence, bridging advanced research with market-ready products.Minister of Economic Affairs Kung Ming-hsin. Credit: TCAMinister Highlights Shift From Hardware Dominance to Practical Industry DeploymentDuring the ceremony, Minister of Economic Affairs Kung Ming-hsin emphasized that while Taiwan maintains a critical global advantage in foundational AI hardware such as semiconductors and servers, the next vital phase involves translating this power into practical applications across all sectors. Under the framework of the government's new major AI infrastructure initiatives, the ministry has established over 50 trial production sites with automated AI capabilities and developed models covering 23 core industries. More than 1,000 consultants have been deployed across the nation to actively assist over 2,600 enterprises in integrating artificial intelligence into their daily operations.Emerging Tech Trends Shape the Future of Edge and Agentic IntelligenceThe second edition successfully guided industrial investments toward the frontier developments of Agentic AI and Edge AI, shifting artificial intelligence from a passive responsive tool to an autonomous partner capable of independent judgment. Driven by strong local integrated circuit design capabilities, more than 430 projects focused on lightweight AI architectures to enable real-time processing directly within terminal devices and industrial machinery. Furthermore, 590 teams integrated open-source environments like GitHub and registered on Crunchbase, significantly elevating the international visibility of the technological ecosystem.Extended Business Matchmaking Initiatives Showcase Commercial Achievements at COMPUTEXTo foster substantial commercial partnerships, organizers featured a dedicated industry matchmaking zone during the finals to link venture capital with startup resources. This promotional effort extended into the COMPUTEX exhibition period, where exclusive matchmaking sessions successfully showcased the winning projects to connect the teams with international buyers and global investors. The Ministry of Economic Affairs plans to continue opening institutional pilot lines to support design verification, prototyping, and unified system integrations, ensuring businesses can seamlessly implement artificial intelligence without developing systems from scratch.The Best AI Awards celebrate global excellence in artificial intelligence and IC design, welcoming submissions from innovative companies and brilliant student teams. Following the success of the 2026 edition—advised by the MOEA, organized by DoIT, and executed by TCA—the prestigious competition is officially transitioning into an annual tradition.Offering substantial grand prizes and unmatched industry exposure, the countdown to Best AI Awards 2027 has already begun. Details on the next submission cycle, prize tiers, and eligibility rules will be released soon. Connect with on LinkedIn for the latest official updates and application alerts. Group Photo of the Best AI Awards 2026 Winners. Credit: TCA

Six months into 2026, the story isn't whether the electronics supply chain has stabilized. It has, broadly. The real story is that it has split into two distinct markets moving in opposite directions, and most procurement teams are still planning as if there's just one. The AI-driven leading edge remains capacity-constrained and pricing-positive, while the mature-node segment is loosening into a genuine buyer's market. Knowing which side of that line each line item on your BOM sits on is the single most useful thing you can do heading into the second half of the year.The Two-Speed Market, BrieflyTSMC is reportedly preparing to raise prices 3–10% on its sub-5nm offerings, and with Nvidia and Apple having already locked in large blocks of capacity through year-end, second-tier buyers are increasingly competing for allocation that may not exist in H2. Memory tells a similar story. Combined output from Samsung, SK Hynix, and Micron is expected to grow sharply by 2030, led by a projected rise in HBM production, but that new capacity doesn't meaningfully arrive until 2027. In the meantime, DRAM and HBM remain the tightest categories in the entire component ecosystem.Mature-node wafer pricing has actually returned to pre-pandemic levels, down 5–8% year-over-year, as Chinese fab capacity comes online and automotive/industrial utilization climbs into the 80–85% range. Consumer electronics demand is stabilizing too, which is easing pressure on mature-node semiconductors and passives.What This Actually Means for Your Procurement StrategyThis is where most H2 outlooks stop short. Here's what to actually do with this picture, category by category.1. Segment your BOM by risk profile, not just by part number.Advanced logic tied to AI-adjacent applications faces a fundamentally different supply reality than commodity discrete or mature-node passives. Treat these as two separate procurement strategies, not one blended approach. A BOM review that groups parts by constrained, stable, or loosening rather than by function or supplier will surface where your actual exposure sits, and it's often not where teams assume.2. Use the mature-node buyer's market now, not later.If you were forced into single-sourcing during the 2021–2023 shortage years, H2 2026 is the window to qualify second sources for those mature-node components while pricing and availability both favor you. This window won't stay open indefinitely. As automotive and industrial utilization keeps climbing toward capacity, the leverage shifts back to suppliers.3. Be strategic, not reactive, on memory buys.Memory is not one uniform story. Leading-edge densities tied to HBM demand carry a real price premium, but previous-generation DDR4 and LPDDR4 may still offer value while pricing is structurally supported mainly at the high end. If your designs can tolerate a prior-generation module, this is the year to lock it in rather than wait and hope for relief that isn't coming until 2027.4. Watch for new procurement categories forming in real time.Optical networking components for AI data centres are moving from niche to mainstream as AI clusters push toward much higher bandwidth per rack. If your roadmap touches high-bandwidth AI infrastructure at all, get ahead of this now. Procurement categories that don't exist yet in your sourcing playbook have a way of becoming urgent overnight once a design win locks them in.5. Rebuild safety stock around true risk, not blanket buffers.Broadly increasing inventory across the board is expensive and imprecise. The more effective move is targeting buffers at the small percentage of components, often a single connector, capacitor, or legacy memory module, that actually drive downtime risk if they disappear. Combine that with forecasting discipline: suppliers increasingly prioritize allocation and pricing based on how credible and consistent your rolling forecasts are, which means forecast accuracy is now a negotiating asset, not just a planning exercise.6. Don't sleep on non-obvious demand drivers.Rising defense spending across Asia-Pacific is quietly adding a new, non-cyclical source of demand for industrial and mature-node electronics, one that doesn't show up in most consumer-electronics-driven forecasts. If your end markets touch defense, aerospace, or industrial automation, factor this in as upside demand pressure, not background noise.The Bottom Line for the Rest of 2026H2 2026 doesn't call for a single supply chain strategy. It calls for two, running in parallel. Where you're constrained, the priorities are allocation planning, forecast credibility, and locking in what capacity you can. Where you're not, the priority is using the current leverage to diversify, qualify alternates, and rebuild resilience before the window closes. Teams that treat this as one undifferentiated “stabilizing market” will miss both opportunities.If you're navigating either side of this, securing allocation on constrained parts or taking advantage of loosening mature-node availability, that's exactly the kind of sourcing challenge our team works through with customers every day. Reach out to your Fusion Worldwide representative and let's talk through your BOM.(Article Sponsored by Howard Tan, Director of Purchasing, China Fusion Worldwide)

Marine debris management is entering a new phase of data-driven applications. Converting years of accumulated coastal imagery into actionable tools for surveying, identification, and monitoring has emerged as a critical challenge in the digitalization of ocean governance.Under the guidance of Taiwan's Ocean Affairs Council (OAC), the National Academy of Marine Research (NAMR) is hosting the "2026 International Marine Debris Image Recognition AI Challenge." Featuring a dataset of over 20,000 real-world marine debris images, the competition invites AI, data science, computer vision, and marine science teams from Taiwan and abroad to participate.The competition is supported by Amazon Web Services (AWS) as the AI technology partner, with model evaluation and competition operations managed through the Industrial Technology Research Institute's (ITRI) AIdea AI Co-Creation Platform. Registration is now open.NAMR sets the challenge: bringing AI to the frontlines of ocean governanceMarine debris has long been a fundamental issue in coastal environmental governance - and one of the most difficult to address in the field. Coastal debris is diverse in type, scattered in distribution, and frequently degraded by sun exposure, seawater erosion, sand burial, and physical damage, making manual surveys and image interpretation highly labor- and time-intensive.To accelerate digital transformation, NAMR has established MDImageNet, an AI-Ready marine debris image dataset covering the ICC19+1, NAMR26+1, and NAMR33+1 marine debris category schemes. The competition draws on NAMR's existing marine debris image dataset, comprising over 20,000 images annotated with YOLO-format bounding boxes. The dataset covers common coastal waste categories including plastic litter, fishing-related debris, and other anthropogenic waste.A "post-mapping" strategy is adopted: participants first train models using the original class labels provided, then map predictions into 20 official recognition categories during inference, with final scoring based on 19+1 primary marine debris target classes.The competition design confronts teams with the real-world constraints of field data - cluttered backgrounds, diverse object classes, and significant appearance variations. By requiring quantitatively evaluated object detection models, the challenge goes beyond open data sharing: it validates whether AI can be transformed into deployable tools built upon existing survey infrastructure.The competition comprises preliminary and final rounds, evaluated primarily on mean Average Precision (mAP) at an IoU threshold of 0.5. A "Best Lightweight Optimization Award" is also offered, using NetScore to balance detection accuracy, model size, and computational complexity-encouraging models suitable for practical deployment in coastal patrols, UAV-based image analysis, and long-term environmental monitoring.AWS cloud resources and AIdea platform power hands-on AI developmentThe competition integrates resources from AWS and ITRI's AIdea AI Co-Creation Platform to support teams throughout model development, training, testing, and evaluation. AWS provides the cloud development environment, offering Amazon SageMaker AI and computing resources for machine learning workflows. Technical workshops are also scheduled to familiarize participants with cloud-based AI development tools and model training pipelines.ITRI's AIdea Platform handles competition execution, dataset support, and automated scoring. The standardized cloud environment and evaluation framework ensures all teams operate under identical conditions, maintaining fairness and reproducibility.The competition is open to high school students, college students, and professionals, with teams of two to five members. Cross-institutional and interdisciplinary collaboration is encouraged, combining expertise in AI, computer vision, data science, and marine science to produce evaluated model outcomes for marine debris recognition.Registration for the "2026 International Marine Debris Image Recognition AI Challenge" is open until August 10. The total prize pool is NT$300,000, with two additional Best Lightweight Optimization Awards.NAMR aims to bring together the AI community, research institutions, academia, and industry to convert marine debris imagery into deployable environmental monitoring models-building Taiwan's AI application experience and marine data foundation for ocean governance.For competition details and registration, visit the official website (link).

Pursuing a PhD might have been the most lucrative decision that Tomasz Matusiak has ever taken.Whilst studying at the Wroclaw University of Science and Technology in Poland's third-largest city, he developed chemical sensors made from ceramic materials based on microplasma generators, and electrical components made from a paste of glass and graphite. Now, Matusiak is using this research to solve a bottleneck that plagues the cutting edge of AI development: moving data between where it is stored in memory and where it is handled in the processing unit (for example, the central processing unit [CPU], which handles arithmetic and logical operations; or more specialised graphics processing units [GPUs], which handle computer graphics and digital images) wastes both time and (electrical) power. This limits the extent to which AI models can be scaled up and, of course, harms the environment.What if one could perform all of the computational tasks right where the data are stored? Matusiak thinks his material can do this, and he has started a company, SemiQa, and produced a system inspired by the human brain, the Analog Neural Network (ANN). Unlike conventional chips, which can reach 80°C and require a cooling system, his ANN system only reaches a maximum of 40°C. SemiQa's goal since its inception at the start of 2025 has been to conquer the universe of data centres, replacing their graphic cards (and the GPUs that power these graphic cards) with ANNs.Matusiak wants to bring back analog processing for its computational advantages. He uses the analogy of a train ride through the countryside. One might look outside the window and see a forest pass one by, followed by a short section alongside a river, before heading back into the forest again. A human brain – the analog system – would see a forest and then not think about it again until it sees a change in the environment (the river), and then once again not actively register the river again until the river has been replaced by the forest. It only processes the changes.But a digital system would constantly process what is outside the window. Analog processing thus saves on energy as it doesn’t process when there hasn't been any change.Likewise, digital processing might allocate a large number of bits to a small integer – for example, even though the number 5 can be expressed in binary with just three bits (101), it might be stored in an 8-bit or a 16-bit structure, where most of the surplus bits are zeroes. Many of the operations performed on these small integers will also result in small integers, so most of the leading zeroes will not change. A lot of memory is wasted.Analog processing can get around this problem by simply storing the 5 in a memory cell as a 5 instead of in eight memory cells as 00000101. (Analog memory cells, unlike digital memory cells, can take on more values than just 0 and 1.)The neural approach is based on a special electrical component called a memristor (short for memory resistor). A traditional resistor follows Ohm's Law, which states that the current (the rate at which electric charge flows) through a conductor is proportional to the difference in voltage (or the difference in electric potential energy, or the work it would take to move a unit of charge provided by, for instance, a battery) across that conductor. Mathematically, Ohm's law is V= IR, where V stands for the voltage, I for the current, and R for the resistance of the conductor, a proportionality constant that indicates how difficult it is for charge to move. The higher the resistance, the lower the current (for a given level of voltage).In a traditional resistor, the resistance doesn't vary with current (or voltage). In a memristor, though, the resistance depends not just on the current (or voltage) but also on the past levels of current running through it (or voltage controlling it). In other words, if the voltage goes up and then goes back down to its earlier level, the current and resistance might not return to their original levels. This ability to take on a range of values of resistance also mean that the memristor can be analog – in other words, that it can represent a range of values and not just a 0 or a 1.In addition to its superior thermal properties, SemiQa's ANN1000 is more power-efficient than other chips, being able to carry out more than 30 TOPS (or 30 trillion operations per second) per Watt of power; standard GPUs or NPUs (neural processing units, which are specialised for AI applications) can only carry out 1-2 TOPS per Watt. (The chip consumes 2.5 Watts of power, and so can carry out roughly 75 TOPS.)It is also naturally faster – ANN1000's latency (the time delay between when the processor requests something from memory to when the processor retrieves it) is 50 times shorter than that of a conventional GPU or NPU.The next step is, of course, commercial-scale production of their chips. They already demonstrated a proof-of-concept of their memristive technology at last year's SEMICON Taiwan, an annual trade show and Asia's largest semiconductor event. They will now create a neural network on silicon and hope to have a product-ready chip tailored to specific applications by the end of 2027. The memristive material, a mixture of organic and inorganic parts, is compatible with CMOS (complementary metal-oxide-semiconductor) technology, which is commonly used in foundries to fabricate chips. Matusiak envisions SemiQa's chips in mission-critical applications where efficient power consumption and processing is highly advantageous. These include autonomous systems, such as drones to be used in war and marine robots. Electric cars can also benefit: GPUs currently account for roughly half the cost of driverless vehicles, and replacing conventional GPUs with SemiQa's chips could reduce the price for consumers whilst maintaining manufacturers' margins. SemiQa also plans to add B2B applications such as data centres to the aforementioned B2C applications. They will tackle this through the ANN2000, a matrix of a thousand smaller ANN1000s.The prize money from the Best AI Awards pales in comparison to the 3 million EUR in pre-seed funding that SemiQa has already raised in Europe. But Matusiak is most grateful for the recognition that the judges have given his company's achievements since they started it just a little more than a year ago. This will also facilitate their collaboration with potential partners – in fact, they are already in talks with two local foundries to deepen their co-operation and scale up production of their chips."If you want something special, you need to work with the special forces," says Matusiak. "Everyone knows that Taiwan is the best in the world."SemiQa also plans to set up a branch office in Taiwan and will potentially hire two business developers in the country in the short term. They also know that they will need more funding, and are looking into perhaps raising money from Taiwanese investors. SemiQa already has a strong relationship with Taiwan, being a member of the Taiwan-Poland Chamber of Commerce and having signed memoranda of understanding with several Taiwanese businesses.The Best AI Awards celebrate global excellence in artificial intelligence and IC design, welcoming submissions from innovative companies and brilliant student teams. Following the success of the 2026 edition—advised by the MOEA, organized by DoIT, and executed by TCA—the prestigious competition is officially transitioning into an annual tradition.Offering substantial grand prizes and unmatched industry exposure, the countdown to Best AI Awards 2027 has already begun. Details on the next submission cycle, prize tiers, and eligibility rules will be released soon. Connect with us on LinkedIn for the latest official updates and application alerts. 

By now, it's common knowledge that artificial intelligence has sped up coding and is now replacing junior software engineers. But can you really trust the code that AI produces?The answer is a clear no. Programmers are still needed to review the code for bugs of all sorts. Maybe the code hallucinates, meaning that it has the right syntax and looks plausible but attempts to, for example, import a library that doesn't exist. Maybe there are functional bugs, where the code simply produces the wrong result because of a faulty algorithm and these are just the simple errors.Moreover, companies are naturally hesitant to release sensitive or proprietary information, such as customer data, to an AI coding tool.Inferara wants to solve these problems. It wants to give you code on which you can rely, free from any vulnerabilities, and it does this by reformulating the code into mathematical notation. This is all done on the user's own computing infrastructure, so that no code or data is ever shared externally.Georgii Plotnikov is the CEO and CTO of Inferara. Originally from Russia, Plotnikov had been working as a software developer for a decade after graduating from university. Roughly five years ago, he started learning more about static code analysis, which can be likened to a real-time spell-checker for code: it is, essentially, early detection for any bugs or security vulnerabilities in the code.He started developing an idea for a new way to turn static code analysis into a mathematics problem at the end of 2023. Around the same time, he started to explore where he could settle down and legally incorporate his company. Plotnikov decided on Japan, sent his business plan and other documents to the country,s government, and after being awarded a startup visa, moved there in the summer of 2024. (Inferara is a relatively young company, incorporated only in October 2024.)Unlike many AI companies, which focus on their product and want to get them out to market as quickly as possible, Inferara is proud to call itself a research-first company. Its main product is not the code checker but rather Inference, which he describes as "a programming language that uses mathematics to ensure code works exactly as intended".This is also known as formal verification, and being formally verified gives programmers and users an additional layer of assurance that, for instance, cryptographic protocols will keep data secure, or that compilers for programming languages will not make mistakes. It's also important for mission-critical processes, such as those in automated (driver-less) driving systems, financial systems, energy plant controls, and medical devices.In a nutshell, formal verification examines all possible states that the (usually finite number of) variables or parameters can take, in order to ensure that the logic is sound. In contrast, simply testing the system with common values that the variables might take might not reach all possible states, especially as the number of variables increases, and it will definitely not reach all possible states when there are an infinite number of variables (or values that the variables can take).Mathematical proofs can group variables together and reduce the total number of states that need to be explored. They can even use mathematical induction to verify an infinitely large number of states.Traditionally, programmers have needed a sophisticated understanding of mathematical logic to manually perform formal verification. Inferara's Inference programming language performs formal verification as one codes (or as AI codes) and makes it possible for even those with no understanding of mathematical logic to guarantee their code's fidelity. Inference's diagnostics are also developed so that both humans and AI coding agents can interpret them and, thus, use them to improve the code's reliability.Inference builds upon and improves the user experience of using Rocq, a piece of software that can assist in mathematical proofs. Plotnikov says that Inference sets itself apart by working what appears to be slowly. Instead of writing code as quickly as possible, it continually checks the code's correctness as it is being generated. This takes more time but, in the end, is more cost-effective, since it requires fewer calls to AI later on. Plotnikov likens this to the slower, more rational and conscious system of thinking described in Daniel Kahneman's bestselling book Thinking, Fast and Slow.Inferara has now taken the next step beyond Inference: It has created Vibe Checker, an operating system that can encapsulate the entire AI-led code-development process. In addition to its own desktop AI agent, Vibe Checker is compatible with the existing, widely-used coding agents of Claude Code, Gemini, and Codex.Most companies currently using AI-assisted coding typically do so via the cloud (i.e., off-premises). Although the code and data is stored under the programmer's domain, all that information traverses multiple external barriers when being run. Vibe Checker provides its own gateway, comprising its own server and the user’s own cloud computing security model (also known as bring-your-own-encryption, bring-your-own-key, or BYOK). Vibe Checker's most data-secure services will host everything on users' own infrastructure, and is appropriate for those users who have the resources to buy their own hardware. There is total data sovereignty: no data ever leaves the user's infrastructure, nothing is ever uploaded to Inferara's servers, and everything can be run even without internet access. An audit trail also logs every action taken by a coding agent.Vibe Checker does more than just check code. It's a multifunctional checker, or task-agnostic, and can audit any AI-generated system for functional errors and security vulnerabilities. Law firms can use it to summarise case files and contracts; researchers and policy analysts can use it to verify their database queries; finance departments can check their tax filings; hospital clinicians can manage their patient records; and banks and insurers can double-check their regulatory submissions.Privacy is essential in all of these aforementioned applications, and Vibe Checker enables on-premise analysis with links and citations referring back to the original source of the information – in other words, no hallucinations.Plotnikov says that Inferara will clearly benefit from the 500,000 NTD prize money from the Best AI Awards. However, the most important reward is the valuable feedback from those working in the industry, telling them that what they are doing makes sense and has commercial value. The award will also help Inferara get its name out and allow them to approach and demonstrate their technology to potential partners; in fact, Inferara is currently in discussions with several companies in Taiwan. In particular, they are interested in working with Taiwan's semiconductor and chip industry, which can provide the hardware supply chain for their product.In the next few months, they plan to deploy Vibe Checker to several companies who will serve as beta-testers, including several Taiwanese companies. They also intend to establish a legal entity in Taiwan, and have plans to work with the Centre of Industry Accelerator and Patent Strategy (IAPS) at the National Yang Ming Chiao Tung University.The Best AI Awards celebrate global excellence in artificial intelligence and IC design, welcoming submissions from innovative companies and brilliant student teams. Following the success of the 2026 edition—advised by the MOEA, organized by DoIT, and executed by TCA—the prestigious competition is officially transitioning into an annual tradition.Offering substantial grand prizes and unmatched industry exposure, the countdown to Best AI Awards 2027 has already begun. Details on the next submission cycle, prize tiers, and eligibility rules will be released soon. Connect with us on LinkedIn for the latest official updates and application alerts.

As artificial intelligence (AI), high-performance computing (HPC), high-speed networking, and edge computing applications continue to expand rapidly, global demand for custom ASIC solutions is rising at an unprecedented pace. Faced with the escalating design complexity and development costs associated with advanced process nodes at 6/5/4/3nm, balancing time-to-market, cost efficiency, and production quality has become a critical challenge for IC design companies and system vendors worldwide.PGC (TPEx: 8227), with over 35 years of expertise in ASIC design services, is a member of the TSMC Design Center Alliance (DCA) and a Synopsys IP OEM Partner. With a track record of more than 1,500 tape-out projects and over 100 tape-outs completed annually, PGC delivers comprehensive capabilities spanning advanced-node design, APR (Automatic Place and Route), back-end design services and tape-out foundry services, and volume production ramp. In response to growing market demand for advanced-node ASIC development, PGC announces the further enhancement of its Customer-Owned Tooling (COT) business model, integrating ASIC design services, IP resources, and semiconductor supply chain ecosystems to help customers shorten chip development cycles, accelerate tape-out, and rapidly secure engineering samples and production capacity.COT Business Model: Balancing Design Ownership with Development EfficiencyThe COT business model enables customers to retain ownership of critical design assets — including IP, EDA tool licenses, and design data — preserving their core intellectual property and technical autonomy while leveraging PGC's professional ASIC design team and proven design flows to jointly complete chip development. Compared to traditional turnkey models, COT effectively reduces long-term NRE (Non-Recurring Engineering) investment, eliminates vendor lock-in, and enhances flexibility for product iteration, multi-project development, and cross-generation platform continuity.In practice, customers adopting the COT model have achieved development cycle reductions of over one month, along with long-term NRE cost savings of more than 10%, giving them greater autonomy and strategic flexibility in product planning and technology roadmap execution.Synopsys IP OEM Partnership: Lowering IP Licensing Barriers and Accelerating DevelopmentAs a Synopsys IP OEM Partner, PGC provides customers with comprehensive Synopsys IP licensing and integration services. Customers can flexibly incorporate market-proven, high-quality IP based on project requirements, simplifying licensing processes, lowering upfront investment thresholds, and accelerating IP integration and verification through PGC's expertise — further shortening ASIC development cycles and time-to-market.ASE Packaging and Test Integration: Bridging Design to Volume ProductionIn the area of packaging and test, PGC has established a close collaboration with ASE Group, integrating advanced packaging and test resources to provide customers with comprehensive production support from wafer to finished product. This collaboration covers BGA, Flip Chip, and Wire Bond packaging and full test services, helping customers accelerate production ramp while ensuring shipping quality and reliability.One-Stop Solution: End-to-End Support from Design to Mass ProductionBeyond ASIC design services, PGC offers a diverse range of prototyping options, including TSMC CyberShuttle (suited for early-stage design verification, leveraging multi-project wafer sharing to reduce prototyping costs) and VIS (Vanguard International Semiconductor) MPW (suited for specialty process or mature node requirements), enabling customers to complete engineering sample verification with maximum flexibility.PGC delivers a comprehensive one-stop solution encompassing ASIC design, IP integration, APR, DFT, tape-out, prototype verification, packaging and test (OSAT), and volume production ramp，complemented by professional back-end design services  and complete tape-out foundry services, helping customers rapidly obtain engineering samples, complete product validation, and seamlessly transition to mass production, significantly compressing time-to-market.PGC CEO Fred Lai stated: "In a market environment where AI and HPC applications continue to drive demand for advanced-node solutions, customers need more than a design service provider — they need a comprehensive partner capable of integrating IP, design, prototyping, and volume production. By enhancing our COT business model and deepening our three-way ecosystem collaboration with TSMC, Synopsys, and ASE, our goal is to help customers reduce their ASIC development cycles by more than 10%, bringing innovative products to market faster."Looking ahead, as demand for AI inference chips, HPC accelerators, and high-speed networking ASICs continues to grow, PGC will continue to expand its advanced-node service capabilities and further extend its customer reach into the US market, empowering global customers to seize opportunities in the advanced-node semiconductor landscape.PGC Boosts COT Model, Integrates TSMC Ecosystem for ASIC Growth. Credit: PGC

The data center industry is undergoing its largest structural transformation in the past decade due to the rapid development of generative AI. As AI models drive growing demand for GPUs, high-speed connectivity, and high-density computing, data center requirements are evolving beyond traditional colocation services to encompass comprehensive upgrades in power supply, cooling, networking, and overall infrastructure architecture. At the recent DIGITIMES 2026 Enterprise Data Center Forum, Chunghwa Telecom Senior Engineer Hsueh Jen-Hao presented "Meeting the AI Challenge: The Evolution of Data Center Requirements and Infrastructure Upgrade Strategies," outlining Chunghwa Telecom's key strategies for responding to the AIDC (AI Data Center) trend and helping enterprises plan their AI computing capacity. Hsueh Jen-Hao noted that power demand per rack has surged from the traditional 2 kW to 5 kW range to 100 kW and even 200 kW. This underscores that the AI era is driving not merely an upgrade of data center equipment, but a paradigm shift across data center design, cooling architecture, energy management, and cross-border network connectivity. AI Servers Drive Higher AIDC Service StandardsHsueh Jen-Hao described AIDC as a "five-star hotel," illustrating the fundamental transformation in the nature of data center services. As AI servers are high-value, power-intensive, and highly sensitive to environmental conditions, data centers must not only operate around the clock without interruption, but also maintain stable temperature and humidity levels, power supply, and network quality, while adjusting environmental conditions in accordance with customers' SLA requirements.To meet the operating environment required by AI servers, Chunghwa Telecom is also upgrading the infrastructure of its data centers. Hsueh Jen-Hao noted that with a single rack often weighing more than 1,250 kilograms, data center floor loading requirements have increased significantly from 500 kg/m2 to 2,000-2,500 kg/m2. Structural specifications are now approaching those of heavy industrial facilities, redefining the conventional concept of an IT data center. Furthermore, the rapid rise in rack power consumption has pushed cooling requirements beyond the limits of traditional air-cooling systems. From Air to Liquid Cooling: Chunghwa Telecom Delivers Customized SolutionsAI computing has driven a dramatic increase in rack power density, from 30 kW-132 kW for NVIDIA H100 clusters to 140 kW per rack for the liquid-cooled GB200 NVL72 architecture. In response to this trend, traditional downflow air-conditioning systems and fan-wall cooling systems, which can support only up to approximately 20 kW, are gradually becoming unable to meet the cooling requirements of next-generation servers.To address the surge in cooling demand driven by AI computing, Chunghwa Telecom is actively introducing liquid-cooling technologies and tailoring solutions to individual customer requirements. From facility planning and design to project management, Chunghwa Telecom offers one-stop services to deliver the essential infrastructure needed for high-density AI computing, including cooling systems, power distribution, and power backup mechanisms. Through flexible modular designs, the data centers can be expanded alongside customers' business growth, satisfying the requirements for large-scale computing and data processing. Hsueh Jen-Hao noted that driven by both the thermal demands of AI servers and international regulations incorporating data center energy performance, liquid cooling solutions are gradually becoming a standard configuration for AIDCs. AIDC Ecosystem Expansion: Green Energy, All-Photonics Networks, and Submarine CablesIn response to the AI wave and the growing adoption of innovative applications, Chunghwa Telecom is not only enhancing cooling technologies within its data centers, but is also pursuing a comprehensive strategy spanning energy, networking, and submarine cable infrastructure. First, Chunghwa Telecom launched its Green Energy AIDC initiative in 2020. As of 2025, approximately 40% of the electricity consumed by its data centers came from renewable energy sources. The company aims to achieve its sustainability goal of powering data centers with 100% renewable electricity by 2030. Second, as cross-regional collaboration and data exchange continue to expand rapidly, high-bandwidth, low-latency connectivity has evolved from a competitive advantage into a fundamental requirement for data centers. To support the development and advancement of internet technologies, Chunghwa Telecom is promoting reference architectures, frameworks, and specifications for next-generation ICT infrastructure centered on all-photonics networks (APN), meeting the increasingly stringent requirements of innovative applications and AI computing for power efficiency, bandwidth, and latency. In addition, Chunghwa Telecom is Taiwan's first and currently only telecommunications operator to serve as a board member of the IOWN Global Forum.Hsueh Jen-Hao noted that the attractiveness of a data center location is directly proportional to the availability of local submarine cable resources. The continued growth of data centers in Hong Kong and Singapore, for example, is largely attributable to their roles as major international submarine cable hubs in Asia. To this end, Chunghwa Telecom has continued to invest in Taiwan's submarine cable infrastructure. On the international front, in addition to the completed SJC2 submarine cable system, the APRICOT system is also scheduled for completion in 2027. To enhance domestic network resilience, the Taiwan-Penghu-Kinmen-Matsu No. 4 submarine cable is expected to be completed in 2026. As these submarine cable projects come online, they will not only significantly strengthen Taiwan's international connectivity, but also provide a solid infrastructure foundation for cross-border AI computing and the deployment of international data centers.From floor loading capacity and liquid-cooling technologies to renewable energy initiatives, all-photonics networks, and submarine cables, Chunghwa Telecom's data center investments in recent years may appear to span different domains. However, they are all guided by the same strategic objective: systematically strengthening data center infrastructure to support enterprise AI adoption, ensure uninterrupted operations, and enhance Taiwan's competitiveness in the AI era. 

Smiths Interconnect, a Molex company, announces its top performing distributors in 2025. The Distribution Awards program honors distributors which have made a meaningful impact on the growth of Smiths Interconnect across its three key regions: the Americas, EMEA, and Asia.Award recipients in each region are selected based on their outstanding performance compared to the previous fiscal year and on outstanding local service and support. This year, the strong commitment and dedication shown by distributors worldwide have resulted in a larger group of recognized companies. Seven distributors in total have been distinguished for their exceptional achievements.In the Americas, FDH Electronic Products Group, LLC. has been named Distributor of the Year for the second consecutive year. This recognition reflects FDH's outstanding performance, strong partnership, and unwavering commitment to delivering exceptional service and support to its customers.Over the past year, FDH achieved impressive sales growth, demonstrating not only market strength but also a deep dedication to driving their mutual success. Their ability to navigate challenges, adapt quickly, and maintain focus on execution has been instrumental in delivering consistent results and strengthening the partnership.The second distributor recognized in the Americas as Highly Commended Distributor for Business Growth 2025 is Arrow Electronics.Through a focused and strategic customer approach, Arrow has delivered impressive business growth, reinforcing their position in driving market expansion and customer engagement.Arrow's commitment to collaboration, responsiveness, and execution has played an important role in achieving these results. Their team has consistently demonstrated the ability to identify opportunities, adapt to evolving customer needs, and deliver value across joint initiatives.In the EMEA region, Smiths Interconnect has recognized two distinct distributors for their outstanding growth throughout the year.RFMW Ltd is recognised for delivering the strongest growth in 2025 across the company's RF component product lines, reflecting exceptional commercial execution and deep customer engagement. Their results in key South European territories were achieved through a close, collaborative partnership that enabled both organisations to navigate a highly competitive landscape effectively.RFMW consistently converted design activity into revenue while expanding presence in target markets, demonstrating a shared commitment to technical excellence, partnership, and sustained value creation.For the Connectors product line, the top performing distributor was Heilind Electronics GmbH, which supported sales growth with a strong focus on the DAC countries.This success was also driven by well-managed inventory levels, enabling fast deliveries and reliable local support for customers.Last but not least, Asia was one of the most active areas from a distribution standpoint. Three key distributors were appointed: Fusoh Shoji Co., Ltd, Bizmile Co. Ltd, and Conn-Tek Electronics Inc.First, Fusoh Shoji Co., Ltd was named Distributor of the Year 2025 for the Fiber Optic and Components product lines. The company has demonstrated outstanding performance in expanding these product lines in Japan, playing a key role in strengthening its market presence and supporting a solid foundation for future growth.Meanwhile, in the Connectors product line, Korea's Bizmile Co. Ltd secured the Distributor of the Year 2025 title. Awarded for its outstanding contribution to business growth, design-in excellence, and value delivery, Bizmile demonstrated exceptional support to key accounts by driving significant growth through strong inventory commitment and strategic project support. The company also excelled in design-in activities, successfully contributing to major defense programs while consistently delivering measurable value to customers. Its strength in commercial execution, strategic account development, and an ecosystem-driven approach has enabled sustained growth, improved profitability, and strong future demand visibility.Rounding out the region's success, Conn-Tek Electronics Inc was named Distributor of the Year 2025 for the Semiconductor Test product line for the second consecutive year. This award recognizes Conn-Tek's exceptional performance across business growth, design-in excellence, and strategic market development. The company achieved remarkable revenue growth in both China and international markets while demonstrating strong leadership in design-in activities with key customers. Furthermore, Conn-Tek experienced significant expansion in high-value product segments—particularly with the DaVinci coaxial test socket—and successfully penetrated new customer markets. Its design-led, partnership-driven approach has delivered sustained growth, improved profitability, and enhanced strategic value across the Asia region.