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NEWS TAGGED EDA
Thursday 16 August 2018
Cadence to open subsidiary in Nanjing
EDA vendor Cadence Design Systems is scheduled to start operating a new subsidiary in Nanjing, China in September, according to industry sources.
Tuesday 26 June 2018
TSMC partners see big revenue gains from advanced process nodes
With TSMC ramping up its 7nm chip output and gearing up for 5nm risk production, the foundry's ecosystem partners including equipment and photomask suppliers, IP developers and EDA...
Friday 2 February 2018
ASE, Cadence deliver SiP EDA solution
Advanced Semiconductor Engineering (ASE) and Cadence Design Systems have collaborated to release a system-in-package (SiP) EDA solution that addresses the challenges of designing...
Tuesday 8 August 2017
Synopsys launches complete HBM2 IP solution offering
EDA vendor Synopsys has introduced its complete DesignWare high bandwidth memory-2 (known as HBM2) IP solution consisting of controller, PHY and verification IP, enabling designers...
Monday 10 July 2017
Globalfoundries 22FDX attracts orders from Shanghai Fudan
Globalfoundries' 22nm FD-SOI process, dubbed 22FDX, has obtained orders from Shanghai Fudan Microelectronics, according to industry sources.
Friday 9 September 2016
Globalfoundries unveils 12nm FD-SOI process
Globalfoundries has unveiled a new 12nm FD-SOI semiconductor technology. Building on the success of its 22FDX offering, the company's next-generation 12FDXplatform is designed for...
Friday 26 February 2016
EDA, IC design service companies positive about 1Q16
EDA and IC design service companies have been approached by many of their customers for design services despite seasonality, and have expressed optimism about their performance in...
Thursday 3 December 2015
Cadence unveils Virtuoso platform for 10nm processes
Cadence Design Systems has announced the delivery of the new Virtuoso advanced-node platform that is enabled for all 10nm FinFET designs. This next-generation custom design platform...
Tuesday 20 October 2015
Mentor Graphics Veloce VirtuaLAB adds protocols for networking designs
Mentor Graphics has announced its Veloce VirtuaLAB Ethernet environment with support for 25Gb, 50Gb and 100Gb Ethernet designs. VirtuaLAB is Mentor Graphics' platform for delivering...
Wednesday 17 April 2013
Globalpress Electronics Summit 2013: Mentor Graphics sees opportunities in FinFETS
Mentor Graphics chairman and CEO Wally Rhines has indicated that Mentor's design for test (DFT) and physical verification tools will be what distinguishes the EDA company in the development...
Saturday 22 December 2012
Global EDA industry prospering: Q&A with Walden Rhines, chairman and CEO of Mentor Graphics
The global EDA (electronic design automation) market has been growing at a rapid pace since the 2008 financial crisis, sustaining a growth rate higher than the industry's average...
Friday 26 October 2012
Mentor Graphics addresses formal verification with Questa
Mentor Graphics recently announced a new formal-based technologies in the Questa Verification Platform that provide mainstream users with the ability to more easily perform exhaustive...
Tuesday 8 May 2012
Apache releases sign-off solution for sub-20nm designs
Ansys subsidiary Apache Design recently introduced its RedHawk-3DX design tool to meet the power, performance and price demands of low-power mobile, high-performance computing, consumer...
Tuesday 8 May 2012
Focus on power efficiency in IC design benefiting Apache
With mobility and smart devices being the hottest trends in the IT industry, power consumption is driving the entire semiconductor food chain, from the manufacturer to the designer...
Tuesday 8 May 2012
Center of gravity shifts for mixed-signal development: Q&A with Ravi Subramanian, CEO of Berkeley Design Automation
Over the next 30 years, the world's middle class (defined as per capita income of more than US$8,000 a year) will grow to include four billion people, meaning that 170 people are...