Data center AI accelerator package power has climbed from about 500W in the A100 generation to roughly 3,500–4,000W for Rubin Ultra-class products expected in 2027, pushing supply current into the thousands of amperes. In conventional frontside power delivery, current must cross the full metal interconnect stack before reaching the transistors, while power and signal lines compete for routing resources. Intel Foundry estimates that raising a single compute package from 1kW to 5kW increases power delivery network I²R losses from 89W to 2,222W, cutting the share of input power reaching the transistors from 66.0% to 41.8%.

DIGITIMES Intelligence has observed that as the performance of AI accelerators and server CPUs continues to advance, chips are increasing not only in compute core counts and I/O channels but also in integration complexity. Higher integration of high-bandwidth memory (HBM), high-speed SerDes, and chiplet designs makes signal transmission, power delivery, and component interconnects within the package far more complex, driving high-end IC substrates toward larger surface areas and higher layer counts.

DIGITIMES has observed that demand for silicon carbide (SiC) power devices has climbed rapidly in recent years as the EV market expands, triggering a massive wave of capacity expansion among SiC substrate makers. However, as SiC substrate capacity continued to surge, actual demand for SiC power devices from the EV sector fell short of expectations. This imbalance triggered a collapse in SiC substrate prices starting in 2024, extending the downward trend through 2026.

DIGITIMES Intelligence said Google used SEMICON Taiwan 2026 to outline the direction of its AI infrastructure strategy, focusing not only on next-generation TPU products but also on how rising AI compute demand is accelerating TPU iteration and deployment.

DIGITIMES Intelligence observes that discussions at the semiconductor sustainability and energy forum during SEMICON Taiwan 2026 centered on two questions: whether Taiwan will have enough electricity to support continued semiconductor expansion driven by AI, and whether that electricity will come from renewable sources.

At SEMICON Taiwan 2026, Google outlined the direction of its AI infrastructure, and DIGITIMES notes that the discussion extended well beyond its next-generation TPU. Rather than focusing on a single chip, Google described how it links large numbers of TPUs into an integrated computing system spanning compute clusters, data centers, and ultimately multiple data centers, while also addressing the power constraints that emerge as the system continues to scale.

SK Hynix is reportedly considering Intel as an additional manufacturing source for high-bandwidth memory (HBM) base dies beginning with the HBM4E generation, a move that could reduce its reliance on TSMC and give the memory maker greater supply and cost flexibility.

DIGITIMES Intelligence forecasts the global semiconductor market will expand from US$791.7 billion in 2025 to US$1.6 trillion in 2026, representing year-on-year growth of 109.1%.

As humanoid robots gradually move from laboratory proofs-of-concept and enter industrial manufacturing and commercial service, their underlying motion control and environmental perception capabilities have become core indicators of product maturity. Major humanoid robot makers are actively seeking the best balance between performance and cost efficiency through architecture restructuring, in-house vertical integration, and supply-chain strategic cooperation.

ASML's latest update suggests High NA EUV is no longer confined to laboratory validation. With 10 systems already operating across four customers worldwide, and three more in shipment or installation, the technology is beginning to enter production ramp-up. The shift matters because adoption now hinges less on optical promise and more on whether chipmakers can justify the added cost.

Taiwanese chip packaging firms are advancing fan-out panel-level packaging (FOPLP) and glass-substrate development as AI processors demand ever-larger reticle sizes and more complex packaging. Their early manufacturing scale, automation progress, and substrate design choices could help determine who controls the next bottlenecks in high-end chip assembly.

Chinese GaN power semiconductor maker Innoscience gained direct access to capital markets after listing in Hong Kong at the end of 2024, giving it fresh funding to expand GaN capacity and technology development.

DIGITIMES observed that as AI systems continued to scale, interconnect requirements inside AI data centers had expanded from chips, packages, and boards to racks, clusters, and eventually inter-data-center connections.

For the past two years, China's AI companies have competed on a single axis: whose model performs best. That contest is starting to give way to a harder one — whether those models can actually run, at scale, on chips made in China, as US restrictions on advanced AI chip exports raise the stakes of that question.

ASIC and GPU shipments will reach a "golden cross" in 2027, with ASIC shipments expected to surpass GPU shipments for the first time at 15.3 million units, DIGITIMES Intelligence analyst Stella Weng said. She also said AI is driving a "qualitative change" in memory architecture inside AI servers.