ASML expects its first advanced semiconductors made using next-generation High-Numerical Aperture (High-NA) extreme ultraviolet (EUV) lithography equipment to ship within months.
Speaking on May 19 at the ITF World 2026 conference hosted by Imec, CEO Christophe Fouquet addressed the cost concerns head-on. He acknowledged the systems' steep upfront price but maintained that their architecture will lower long-term patterning costs — replacing complex multi-patterning steps with single-exposure resolution as the industry moves into the sub-2-nanometer Angstrom era.
Intel charges ahead, TSMC holds back
The competitive dynamics look nothing like they did a decade ago, when Intel's delayed adoption of standard EUV tools ceded dominant market share to TSMC. Today, Intel is the most aggressive adopter of High-NA technology, having already run roughly 300,000 trial wafers through its first two systems. TSMC, by contrast, has taken a cost-conscious stance and opted to bypass High-NA for its latest process nodes.
A US$400 million bet on proof-of-concept
The barrier to universal adoption is straightforward: cost. Reuters reports that a single High-NA system carries a price tag of up to US$400 million. GuruFocus data puts ASML's price-to-earnings (P/E) ratio at 47.07x, signaling intense investor expectations for near-term commercial validation. The first High-NA memory and logic chips due in the coming months will be a critical test — one that must convince hesitant clients like TSMC and Samsung Electronics that the tool's 66% reduction in feature sizes justifies the price.
AI tailwinds, foundry bottlenecks
The AI boom has transformed High-NA tools from niche logic machinery into essential, cross-sector capital assets. An extended data center storage supercycle projected to last through 2028 is already driving memory giants like SK Hynix to sign multi-billion-dollar equipment contracts.
High-NA lithography will be central to fabricating next-generation high-bandwidth memory (HBM) modules and advanced data-center DRAM cells. Fouquet pushed back on suggestions that ASML is the bottleneck. The real constraint, he argued, lies with the foundries — which must expand cleanrooms and procure more lithography systems to keep up with an AI economy set to grow global chip sales by 20% annually in the years ahead.
Article edited by Jerry Chen
