As AI drives demand for advanced computing infrastructure, chip architectures are at a crossroads. While proprietary instruction set architectures (ISAs) like x86 and Arm dominate the market, their closed nature and high licensing fees increasingly hinder innovation.
Qualcomm faces its biggest obstacle not from Nvidia or AMD, but from Arm in entering the data-center server processor space amid ongoing patent disputes.
Meanwhile, the open-source, modular RISC-V architecture is gaining traction with its flexibility and customization potential, poised to disrupt existing market dynamics.
Allen Wu, former chairman of Arm China who has fully committed to RISC-V after leaving Arm, told Yicai that x86 was king in the PC era, Arm ruled the mobile age, and he believes RISC-V will be the king in the AI era.
Tenstorrent and Qualcomm bet on RISC-V
AI chip startup Tenstorrent, led by AMD's "Zen" CPU architect Jim Keller, aims to challenge Nvidia's dominance with a radically different approach based on RISC-V. Keller claims Tenstorrent's RISC-V-based products could cost 5-10x less than GPUs while delivering comparable performance.
Qualcomm also sees strong potential in RISC-V for AI workloads. In December 2025, it quietly acquired Ventana Micro Systems, a lesser-known chip developer focused on high-performance RISC-V chiplets and CPU/platform IP licensing. Although financial details were undisclosed, industry observers interpret this move as Qualcomm's strategic bet on servers through RISC-V.
Given Qualcomm's core chips still rely heavily on Arm ISAs and its protracted legal battles with Arm, the company evidently wants to reduce dependence on the Arm ecosystem and secure more autonomous resources by cultivating RISC-V as a "second path."
Google embraces RISC-V for large-scale data centers
At a recent RISC-V Summit, Martin Dixon, Google's director of engineering, delivered an insightful keynote outlining opportunities, challenges, and prerequisites for deploying RISC-V at data center scale.
Dixon cited Google's successful transition to Arm-based servers as a foundation for integrating RISC-V into its massive compute infrastructure, underscoring Google's commitment to open architectures and positioning RISC-V as a key pillar for future hyperscale computing.
Google's heterogeneous computing journey began on general-purpose x86 platforms nearly three decades ago.
The company experimented with Arm in the mid-2010s following the 2014 release of Arm server specifications. Today, Google's data centers run a mix of x86, Arm, and emerging architectures, including early-stage RISC-V components.
Dixon stressed that heterogeneity and specialization are critical to overcoming Moore's Law slowdowns, enabling greater efficiency and performance at scale. He praised RISC-V's openness and customization promise but warned that without standards, it becomes a "double-edged sword." He highlighted initiatives like RVA23 and forthcoming RISC-V server platform specs as essential benchmarks to ensure compatibility for large deployments.
Four keys to RISC-V success
Using a vivid "road trip" analogy, Dixon outlined four keys to RISC-V success.
First, a "roadmap" requiring standardized specs mandating features such as branch recording—akin to Intel's LBR or Arm's BRBE—side-channel hardened encryption, and MMU support to guarantee security.
Second, a "cool car": a high-performance server-grade SoC with at least 64 cores, each supporting over 4GB memory, prioritizing performance, reliability, and maintainability.
Third, the "Beyonce Rule," a playful nod to Google's internal motto: "If you liked it, then you shoulda put a test on it." Critical functions must undergo comprehensive testing to simplify multi-architecture porting.
Finally, strong partnerships foster vibrant community collaboration to build a robust software ecosystem that "compiles and runs out of the box."
Google's RISC-V roadmap
Looking ahead, Google actively participates in RISC-V International's standardization efforts around quality of service (QoS) and RVA23, serves as a founding member of RISE, and accelerates upstream Linux and LLVM development. To automate processes, Google applies its Gemini AI model to analyze and classify 40,000 Arm migration patches for future automated changes.
Dixon summarized RISC-V's four imperatives: establish server standards, deliver powerful SoCs, expand testing coverage, and embrace AI aggressively.
Article edited by Jerry Chen
