France's CEA-Leti, a leading European semiconductor research institute, outlined ambitious strategies to address critical AI hardware bottlenecks through advanced silicon photonics, 3D integration, and wide bandgap technologies during a high-profile event with Taiwanese industry leaders.
The collaboration-focused symposium highlighted CEA-Leti's push to strengthen ties with Taiwan's semiconductor ecosystem as computing demands from generative AI continue to strain data center infrastructure.
During his keynote, Sébastien Dauvé, CEO of CEA-Leti, emphasized the organization's foundational commitment to developing low-power solutions. He identified data communication as a significant constraint for both bandwidth and power consumption in modern computing systems.
Silicon photonics tackles AI interconnect challenge
Eléonore Hardy, Silicon Photonics Partnership Manager at CEA-Leti, outlined the institute's roadmap for overcoming communication bottlenecks in AI systems through advanced photonic integration. Following Nvidia's recent adoption of photonics technology, CEA-Leti is accelerating development of more efficient modulators, improved co-packaged interfaces, and lower-cost industrial solutions.
Hardy noted that optical integration would progressively move closer to compute chips to reduce latency and increase bandwidth.
The research center has developed collective direct bonding techniques for integrating III-V materials onto silicon photonics platforms, enabling efficient laser integration for high-speed data transmission. Hardy revealed a prototype with multi-chip heads bonded onto a silicon photonics active interposer featuring photodiodes and microring resonators for routing, creating a compact, energy-efficient optical network on chip.
Insulated recessed-gate GaN power transistors have the potential to redefine power conversion systems for solar panels, on-board chargers, USB-C chargers, and data centers. (Credit: CEA-Leti)
GaN innovation drives data center power efficiency
Martin Gallezot, Deputy Head of Silicon Components Division, discussed CEA-Leti's work on gallium nitride (GaN) power electronics to address another critical AI infrastructure challenge: energy efficiency in data centers.
Gallezot explained that current power conversion processes result in approximately 40% power loss when converting from high voltage to the chip level. CEA-Leti aims to dramatically reduce this figure to about 7% through innovative approaches.
The institute is developing monolithic integrated GaN transformers capable of more efficient voltage conversion, potentially yielding substantial energy savings for data centers that increasingly consume hundreds of megawatts of power. CEA-Leti's proprietary MIS-gate GaN technology offers advantages over current commercial "p-GaN" solutions, including higher voltage tolerance (1500V versus industry-standard 1200V), lower temperature dependency, and critically for data centers, higher lifetime reliability.
3D integration enables heterogeneous computing
The event showcased CEA-Leti's extensive experience in 3D integration technologies, with a focus on the 1-10 micron range technologies crucial for HPC architectures.
Gallezot highlighted the importance of mixing CMOS with other technologies, such as sensors, III-V materials, and photonics for next-generation computing systems. This heterogeneous integration approach aims to overcome the limitations of traditional CMOS scaling.
CEA-Leti has progressed significantly with chip stacking technologies, demonstrating a functional architecture with six chip heads containing 16 cores each (96 interfaces total) stacked on an active interposer. This approach enables independent power management for each chip head and maintains cache coherence between them.
Olivier Thomas, Deputy Head of the Digital IC Division, explained how the modularity and scalability of chiplet design allowed CEA-Leti to develop a comprehensive solution for a European car manufacturer, covering requirements for vehicles across different market segments with varying ADAS and infotainment needs.
Photonics West papers will detail processing LEDs directly on 200 mm silicon substrates and minimizing carrier-diffusion length. (Credit: CEA-Leti)
MicroLEDs offer new AI connectivity solutions
Vygintas Jankus, MicroLED Partnership Manager, described how microLED technology could address AI interconnect challenges through parallel optical communications.
Jankus positioned microLED interconnects as a potential solution for AI and high-performance computing connectivity challenges, suggesting they could complement silicon photonics for specific applications like point-to-point connections up to 10 meters.
While microLED interconnects would operate at lower rates per channel than silicon photonics, massive parallelization could yield better overall bandwidth and latency characteristics. The technology benefits from CEA-Leti's capability to process these systems on 200-300mm wafers and their ability to operate at high temperatures (up to 150°C), allowing deployment near heat-generating GPUs in data centers.
Strategic partnership approach strengthens innovation
The institute's innovation track record includes creating the silicon-controlled rectifier now found in every car and smartphone, and developing the Smart Cut process used by Soitec—one of 80 startups CEA-Leti has helped launch. A new 2,000-square-meter state-of-the-art clean room facility will be operational by mid-July 2025, further expanding its research capabilities.
As AI continues to drive unprecedented compute demands, CEA-Leti's technological roadmap and partnership approach provide a distinctive European perspective on hardware innovation while actively engaging with Taiwan's world-leading semiconductor ecosystem.
Article translated by Vyra Wu and edited by Jerry Chen
