Imec unveils a publicly accessible 'virtual fab' in an effort to realize net zero in chip fabrication

Misha Lu, DIGITIMES Asia, Taipei 0

Belgium-based semiconductor research center Imec has launched on November 14 a freely accessible version of its web application imec.netzero virtual fab. Imec developed imec.netzero to accurately quantify the environmental impact of IC manufacturing, utilizing data from Imec's own physical fab where it explores environmentally friendly process solutions such as the reduction of fluorinated etch gases, the maximization of EUV scanner throughput and the reduction of hydrogen and water consumption.

According to Imec, the virtual fab follows the Life-Cycle Assessment methodology to collect and analyze data on the resources used in each process step of chip fabrication, including energy, materials, chemicals and gases. With the release of imec.netzero's public version, the research institute aims to reach a broader audience beyond the semiconductor supply chain, such as environmental researchers and policymakers seeking industry impact data.

Compared to the private version, the public version offers access to the same fab models and process databases, but is restricted to current technologies and Scope 1+2. Nevertheless, Imec indicates that it offers insights into data otherwise inaccessible to the public, such as visual presentations of CO2 emission, electrical energy consumption or total water usage for various logic and memory technologies from 28nm onward.

As CO2 emissions associated with IC manufacturing are expected to quadruple in the next decade as a result of the growing complexity of advanced technologies and the increasing volume of wafers produced. Imec's Sustainable Semiconductor Technologies and Systems (SSTS) program was launched in 2021 in this context, partly aiming to provide actionable data for the industry to enable impact assessment during process and flow development. As a part of the SSTS program, imec's virtual fab tool previously demonstrated that lithography and etch processes were responsible for 45% of the Scope 1 and Scope 2 emissions associated with 3nm logic process, while showing EUV lithography's advantages in limiting carbon dioxide equivalent (CO2eq) emissions associated with multi-patterning techniques.