TSMC is involved in an R&D project led by Nvidia to use its silicon photonic (SiPh) integration technology called COUPE (compact universal photonic engine) for graphics hardware to combine multiple AI GPUs, according to industry sources.
Sources revealed that SiPh chip and CMOS processes go through co-packaged optics (CPO) technology integration, which can connect multiple advanced GPUs with chip-on-wafer-on-substrate (CoWoS) 2.5D IC packaging. Coupled with the low-latency advantage of optical data transmission and through advanced packaging technology such as TSMC's COUPE, signal loss is significantly reduced and even allows for the combination of multiple AI GPUs to form an ultra-large GPU set.
The R&D project with Nvidia and TSMC will reportedly take several years and will have to wait until the SiPh ecosystem matures.
According to sources, Intel previously developed its own SiPh plan that focused on the integration of laser light modules containing compound semiconductor components, which Taiwanese epiwafer maker LandMark Optoelectronics began working on quite early.
However, the sources revealed that the advanced packaging model TSMC has negotiated with potential customers regarding COUPE will only retain the optical channel; the laser light transceiver portion will be placed externally.
This architecture will have a high yield rate and will avoid using Intel SiPh patents. Additionally, with TSMC's long-establish success in using CoWoS packaging in high-performance computing (HPC), HPC and advanced networking switch chips could use the "COUPE+CoWoS" heterogeneous integration method.
The sources noted that the formation of an ultra-large GPU chipset through the combining of multiple top-level AI GPUs through COUPE would be considered a single GPU from an operational standpoint. As a result, it would not need to follow Intel's highly difficult integration method, which integrates the laser light source and requires more consideration for the compound semiconductor's laser chip. TSMC's advanced packaging technology provides customers with more flexibility, the sources added.
The sources pointed out that TSMC's advanced packaging customers not only include Nvidia, but also AMD/Xilinx - who has been keen on obtaining SiPh patents - as well as Broadcom, Cisco, and Marvell Technology.
It was previously reported that TSMC discussed a partnership with Luxtera (now a subsidiary of Cisco) back in 2007 when it was trying to catch up with Intel's SiPh plan. However, at the time chip makers believed the cost of CoWoS was too high and instead intended to seek partnerships with OSATs.
Judging from the advanced packaging technology platforms of leading OSATs, including ASE Technology and its subsidiary Siliconware Precision Industries (SPIL), CPO has become one of the representatives of advanced packaging.
Market research group Yole estimates that the SiPh module market will grow to US$4 billion in 2024, up from US$455 million in 2018, at a compound annual growth rate (CAGR) of 44.5%. Other research organizations have predicted a CAGR of over 50%, driven by ongoing computing, performance, and transmission speed upgrades by data centers, AI chips, and supercomputers.
Article translated by Eifeh Strom
