Bits + chips
Cadence DDR5 IP test chip runs with Micron prototype DRAM
Jessie Shen, DIGITIMES, Taipei

Cadence has disclosed a test chip containing next-generation DDR5 memory interface IP, which operates with Micron Technology's prototype DRAM chips. The test chip was fabricated in TSMC's 7nm process, containing both the controller and PHY, according...

The article you are trying to open requires News database subscription. Please sign in if you wish to continue.
Realtime news
© 2019 DIGITIMES Inc. All rights reserved.
Please do not republish, publicly broadcast or publicly transmit content from this website without written permission from DIGITIMES Inc. Please contact us if you have any questions.