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ACE puts wafer-level packaging on Powerchip DDR

Carol C.Y. Hsu, Hsinchu; Noah Sauve, DIGITIMES Asia 0

At the end of January, Advanced Chip Engineering Technology (ACE) will begin applying its WLCSP (wafer-level chip-scale package) burn-in, packaging and testing solution to 256Mbit DDR (double data rate) SDRAM for Powerchip Semiconductor (PSC).

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