As AI-driven high-performance computing (HPC) and chip-to-chip optical interconnects continue to see rapid growth, Hauman Technologies, a leader in test and measurement solutions, has introduced a breakthrough GHz-class, massively parallel bandwidth testing technology in collaboration with AUO Corporation. Designed to address testing efficiency and throughput bottlenecks for next-generation optical communication light sources, the technology made its official debut at SEMICON Taiwan on September 2.Overcoming Mass-Production Bottlenecks with Parallel High-Speed Testing For years, high-frequency characterization of Micro LED chips has relied on time-consuming, die-by-die measurement procedures. While these methods are well suited to detailed device characterization, their limited throughput presents a major challenge for industrial-scale production and broader commercial adoption.Hauman's newly unveiled Micro LED response-time measurement technology addresses this challenge by enabling simultaneous, parallel high-speed testing across multiple dies. With temporal resolution down to 20 picoseconds (ps), the technology captures the transient optical response of individual light sources at different time intervals, enabling key bandwidth-related parameters to be derived without conventional dynamic scanning.By shifting high-speed characterization from sequential measurement toward parallel acquisition, Hauman aims to bring die-level high-speed screening closer to the throughput requirements of semiconductor manufacturing. Advancing Optical Interconnect Testing in Collaboration with AUOThe collaboration combines Hauman's 20-picosecond temporal resolution and high-throughput parallel measurement capabilities with AUO's expertise in optoelectronic integration, Micro LED mass transfer, and low-power optical engines.Together, the companies are working to optimize Known Good Die (KGD) screening for optical communication devices, supporting next-generation AI data centers and "wide-and-slow" optical interconnect architectures."Our latest technology represents a major step forward in high-frequency testing throughput and the viability of production-scale deployment," said Ying-Chu Lin, Vice President of Hauman's Semiconductor Business Division. By enabling parallel measurement across multiple dies while maintaining die-level visibility, we aim to bring high-speed optical characterization closer to the requirements of semiconductor manufacturing.We look forward to working with semiconductor, optoelectronic device, and packaging and testing industry partners to further advance high-throughput optical measurement for next-generation optical interconnects. For more information, please visit Hauman Technologies. Credit: Hauman Technologies

As AI continues to accelerate demand for high-speed optical connectivity, technologies such as silicon photonics, CPO, LPO, NPO and OCS are moving rapidly toward commercial deployment. The next challenge is turning these technologies into scalable, high-yield production.At SEMICON Taiwan 2026, September 2–4 in Taipei, ficonTEC will showcase its intelligent automation solutions at Booth R8124, highlighting how precision automation, assembly and testing can help photonics companies move from advanced technologies to volume production.From assembly and test to intelligent manufacturingAs photonic devices become more complex and volumes increase, manufacturing requires greater precision, repeatability and throughput. ficonTEC's solutions address key stages of the process, including automated assembly, active alignment, fiber preparation and electro-optical testing, with a focus on connecting these capabilities into scalable production environments.The company's presence at SEMICON Taiwan will focus on a key industry question: How can photonics scale at the speed required by AI?The topic will also be explored during the Silicon Photonics Global Summit, held alongside SEMICON Taiwan.ficonTEC's André Lalonde will present "AI Is Scaling Faster Than Test – Rethinking Wafer, Chip and Module Test for the Photonics Era," addressing the evolving requirements for wafer-,chip-and module-level testing.On September 3, Moritz Seyfried will present "Intelligent Manufacturing for AI at Scale," examining how manufacturing intelligence can support the growing production requirements of AI-driven photonics.Together, the exhibition and presentations highlight ficonTEC's focus on connecting assembly, test and manufacturing intelligence to help the photonics industry transition from engineering development to high-volume production.As AI infrastructure continues to scale, the ability to manufacture photonic technologies with the required precision, yield and throughput will become increasingly important.AI is scaling fast. Photonics must scale with it.

Toward Technologies, Inc. concluded its participation in SEMICON Taiwan 2026, held from September 2 to 4 at Taipei Nangang Exhibition Center Hall 1. Under the theme "RELAY, REDEFINED.," the company showcased a broader switching technology portfolio at booth K3168 and demonstrated its transition from a traditional relay supplier to an advanced switching solution partner.Toward presented high-speed and RF switching technologies, Opto-SiC MOSFET relays, reed relays, solid-state relays, high-speed inductors and modularized switching solutions. The exhibition highlighted the company's capabilities from individual components to integrated switching architectures for semiconductor testing, ATE, probe cards, load boards, RF test, AI/HPC, EV/BMS and high-voltage measurement applications.As AI/HPC, high-speed computing, advanced semiconductor testing, EV/BMS and high-voltage electronics continue to develop, switching components must meet increasingly demanding requirements for frequency performance, signal integrity, low leakage, isolation, switching speed, channel density and system integration. Toward's product portfolio is designed to address these needs across high-frequency, high-voltage and power-related test systems.Broadband Conical Inductor Supports High-Frequency Test InterfacesA featured product was Toward's Broadband Conical Inductor, developed for RF and semiconductor test applications. The solution supports frequencies up to 60 GHz and targets RF/microwave, high-speed semiconductor testing and advanced test interfaces. It can be used in bias tees, DC bias injection networks, RF chokes and broadband test interfaces.For probe cards, load boards, RF test fixtures and other high-frequency platforms, introducing DC bias while minimizing its effect on the RF signal path is an important design challenge. By combining the Broadband Conical Inductor with switching technology, Toward is extending its capabilities from a single relay component to RF signal paths, bias networks and system-level switching architectures.Toward also displayed a Broadband Conical Inductor Module based on its AI-0260 series inductor and ALC series modules. The solution illustrates the company's ability to connect high-frequency component technology with high-speed I/O and test platform integration.Opto-SiC MOSFET Relay Targets High-Voltage TestingToward's Opto-SiC MOSFET Relay is designed for EV, BMS, power semiconductor and high-voltage electronic systems. The product integrates a silicon carbide MOSFET with an optically coupled control architecture. It retains key solid-state relay advantages, including no mechanical contacts, long operating life and high-speed switching, while extending load-voltage capability to the kV range.The relay targets high-voltage testing, measurement-path switching and automated test applications. It supports Toward's strategy of developing switching technologies for electrification and power semiconductor test systems, in addition to conventional relay applications.Multi-Technology Platform Supports Customer DevelopmentToward also presented reed relays, RF MEMS, solid-state relays, high-speed inductor solutions and modularized switching solutions. Different technologies offer different advantages, including low contact resistance, high reliability, compact design, low leakage, high-frequency switching performance and high-voltage capability. This multi-technology platform allows customers to select a switching architecture according to their application requirements rather than being limited to one relay type.As semiconductor test and ATE architectures become more complex, customers need more than a relay datasheet. Toward provides capabilities in relay design, RF and high-speed technology, silicon carbide, packaging, manufacturing, testing and module integration. Its support can extend from application requirements and component selection to sample verification, switching module development and production introduction.This component-to-subsystem approach helps Toward address signal routing, RF path design, bias networks, isolation, channel density and mechanical integration. The company aims to help customers develop switching solutions that match the electrical, thermal, mechanical and testing conditions of each target system.International Collaboration and Future GrowthToward Chairman Hsu said the 2026 event was the company's most successful SEMICON Taiwan participation in more than a decade. He noted that many of the products displayed were developed for future applications and that the company's technology investments are intended to support growth over the next 10 to 20 years.Business partners from Italy, Germany, the United Kingdom, Japan and Singapore also visited Toward's booth. Their participation reflected the company's expanding international network. Toward plans to deepen cooperation with customers and technology partners while strengthening its high-speed, RF, high-voltage, power and modularized switching capabilities.Looking ahead, Toward will continue developing solutions for semiconductor test, AI/HPC, EV/BMS, aerospace and defense, industrial automation and medical devices. Through the message "RELAY, REDEFINED.," the company aims to redefine the role of relays in next-generation electronics and semiconductor test systems and to support practical technology deployment with customers and industry partners. For more information, visit Toward Technologies.Toward Technologies executives at SEMICON Taiwan 2026 in Taipei. Credit: Toward Technologies 

DAS Environmental Experts continues to expand its capabilities in Taiwan and is presenting another new product at SEMICON Taiwan. Against the backdrop of ongoing investments by the Taiwanese semiconductor industry and rising customer demand for local engineering, project management, and service capabilities, DAS Taiwan is expanding its existing Hsinchu office to approximately twice its current size. In doing so, the company is creating the physical conditions necessary for its planned further expansion of personnel and the next phase of growth in the Taiwanese market. DAS Taiwan already employs around 380 people. Looking ahead, the expansion will provide capacity for a workforce increase of about 30 percent. The expansion will take place at the existing location on the same floor. The name and address of the Hsinchu Office will remain unchanged. It is therefore not a new location, but rather part of the ongoing expansion of DAS Environmental Experts' existing organization in Taiwan.ALCEA demonstrates Taiwan's local engineering and innovation strengthIn addition to expanding its Hsinchu office, DAS Environmental Expert is using this year's SEMICON Taiwan to introduce ALCEA, a new solution for the secondary treatment of nitrogen oxides in semiconductor manufacturing. ALCEA was developed in collaboration with the Industrial Technology Research Institute (ITRI), with DAS Environmental Expert's Taiwan-based engineering team playing a central role. The system integrates directly into existing waste air systems and can reduce NOx emissions by up to 95 percent without requiring additional floor space in the subfab. This new product thus demonstrates how DAS Environmental Experts combines its proximity to customers and research partners in Taiwan with the company's technological expertise.DAS grows alongside its customers in taiwan's semiconductor marketIn recent years, Taiwan has become one of the most important markets for DAS Environmental Experts. As semiconductor production has expanded and customers have increased their investments, demand for local technical expertise, reliable project execution and service support has also grown. DAS Taiwan has responded by continuously expanding its organisation, establishing new functions and strengthening existing teams."Taiwan is one of the most important growth markets for DAS Environmental Experts. Our customers continue to invest in new and existing semiconductor capacity and expect engineering, project execution and service support directly on site. We are therefore investing consistently in our local organisation and technical capabilities," says Alex Shen, Senior Vice President DAS Asia and General Manager DAS Taiwan. "The expansion in Hsinchu creates the conditions needed to continue growing our team and provide even more comprehensive support to our customers. At the same time, we are advancing our solutions for reducing PFC and NOx emissions and strengthening our local engineering and manufacturing expertise. This allows us to grow alongside our customers and support their long-term expansion in Taiwan."Local expertise for growing semiconductor capacityFor DAS, its growing presence in Taiwan is closely linked to the needs of the semiconductor industry. New and expanded production capacities not only increase the demand for high-performance waste gas treatment and environmental technologies; at the same time, local engineering expertise, reliable project management, and readily available service capabilities are becoming increasingly important to customers.DAS is therefore continuously expanding its capabilities in Taiwan in line with these requirements. In addition to engineering, project execution and service, the company is advancing its solutions for reducing PFC and NOx emissions and strengthening its local manufacturing capabilities. The digitalisation of internal processes, including the introduction of an ERP system, supports the organisation's continued scaling. This stronger local presence enables DAS to support customers directly on site throughout the various stages of their investment and production projects. Short response times, local technical expertise and growing project and service capacity are intended to help implement new requirements quickly and support the reliable operation of installed systems.New working environment supports collaboration and further workforce growthThe expansion approximately doubles the size of the Hsinchu Office. The new premises provide additional workspaces and meeting areas designed to facilitate collaboration between the location's growing teams and different functions. At the same time, DAS Taiwan is investing in a working environment that supports the recruitment, development and long-term retention of qualified employees. In addition to open-plan workspaces and further meeting rooms, the facilities include quiet areas, a wellness and nursing room, and the multifunctional "DAS Tree Zone" for informal meetings, team activities and wellbeing programmes. Abundant natural light and flexible-use spaces are designed to promote collaboration, wellbeing and productivity. The enhanced working environment forms part of DAS Taiwan's long-term growth and talent strategy. In a dynamic semiconductor market, access to qualified engineering, project and service professionals is essential to delivering additional customer projects reliably and continuing to scale the local organisation.Taiwan as a key pillar of DAS's international operationsThe expanded office space is located in the immediate vicinity of the existing Innovation & Support Center (ISC) and forms part of the location's continued development. The ISC provides the technical infrastructure for system demonstrations and test setups and is also used for customer meetings and the training of service technicians. The additional office space now creates the capacity to employ more design engineers, development engineers and other engineering specialists at the location. This will enable development, engineering, technical support and direct customer engagement to be integrated even more closely in the future. For DAS, the development of its Taiwan operations reflects the company's commitment to evolving its organisation in parallel with the investments and requirements of its semiconductor customers. By combining global technological expertise with local engineering, project execution, manufacturing and service capabilities, the company can reliably support customers as their production capacity grows.With a stronger local organization and continuously expanding technical capabilities, DAS is thereby laying the groundwork to support its customers in Taiwan over the long term, even during the semiconductor industry's next phase of growth. Requirements from the Taiwanese market can be addressed immediately on-site and translated into technical solutions in collaboration with the engineering teams at the Dresden headquarters. In this way, DAS Environmental Expert combines the technological and development expertise from Dresden with the market knowledge and direct customer proximity of the team in Taiwan. The new ALCEA product, for example, demonstrates how this collaboration works. This new abatement product once again shows how ideas and requirements from the local market are directly incorporated into the further development of technological solutions. For more information, please visit DAS Official Website.DAS Founder-Dr. Horst Reichardt & DAS Taiwan General Manager-Alex Shen. Credit: DAS Environmental ExpertsGroup Photo of the DAS Team. Credit: DAS Environmental Experts

As AI, high-performance computing (HPC), and advanced packaging continue to move toward higher levels of power integration, chip power consumption is rising rapidly. Thermal management has therefore become a critical factor affecting performance, reliability, and system design. World Diamond Technology is advancing its large-area diamond growth technology and accelerating the mass production of 300 mm diamond wafers to address the thermal management needs of AI chips and advanced packaging. Five Key Priorities for Mass ProductionThe 300 mm wafer is currently the mainstream format in advanced semiconductor manufacturing. Scaling diamond materials from conventional smaller sizes to 300 mm involves far more than simply increasing the surface area. It also presents multiple technical challenges related to large-area material processing, uniformity, thickness, flatness, internal stress, and surface quality. World Diamond Technology has continued to advance its large-area diamond growth technology and has secured a Taiwan patent (TW Patent: I840846). Its mass-production strategy focuses on five key priorities:(1)Optimizing the diamond growth process through proprietary WDCVDTM diamond growth technology to ensure consistency across large-area wafers.(2)Precisely controlling wafer thickness and uniformity to meet the stringent requirements of advanced packaging thermal management modules.(3)Strengthening flatness and internal stress management to improve yield and reliability.(4)Optimizing surface quality and process consistency to minimize defects.(5)Continuously improving production yield and capacity while establishing a stable supply chain to support customers' volume-production requirements. By advancing toward the 300 mm format, World Diamond Technology aims to increase the potential for integrating diamond materials with existing semiconductor processes and wafer-level application platforms, enabling diamond to progress from a specialty material toward large-scale adoption across the semiconductor industry. Advantages of Diamond MaterialsDiamond offers multiple advantages as a thermal management material. Its thermal conductivity can exceed 1,500 W/(m·K), significantly outperforming conventional heat-dissipation materials. Diamond also features an extremely low coefficient of thermal expansion, helping substantially improve device reliability.In addition, diamond delivers exceptional hardness, wear resistance, high-temperature durability, and chemical stability. These properties enable it to resist corrosion, operate reliably in high-temperature environments, extend product service life, and reduce the total cost of ownership. Targeting AI Chips and Advanced Packaging ApplicationsWorld Diamond Technology's  300 mm diamond wafers will focus on high-power, high-heat-flux semiconductor applications, including:(1)AI GPUs and HPC systems(2)Data centers and servers(3)2.5D and 3D advanced packaging(4)High-power laser devices(5)Automotive electronics and power modules As advanced packaging architectures become increasingly complex, thermal management is evolving from conventional system-level cooling toward package-level, device-level, and even wafer-level solutions. Consequently, the importance of high-thermal-conductivity materials will continue to grow. Diamond Technology Powering a High-Efficiency FutureWorld Diamond Technology stated that the 300 mm diamond wafer represents an important milestone in the company's efforts to industrialize large-area diamond materials. In the next phase, the company will continue to focus on process stabilization, yield improvement, specification standardization, customer validation, and the establishment of volume-production capabilities. It will also actively pursue collaboration with semiconductor manufacturers, advanced packaging companies, thermal module suppliers, and end-system providers. To meet the rapidly growing thermal management demands of the AI era, World Diamond Technology will continue to advance diamond materials from material development to practical semiconductor applications. The company is accelerating the establishment of a comprehensive technology portfolio spanning diamond wafers, diamond lids, diamond heat spreaders, and system-level thermal management solutions, positioning itself to capture opportunities in the next generation of high-power chips and advanced packaging. Discover the latest developments in diamond wafer technology at SEMICON Taiwan 2026. We cordially invite you to visit World Diamond Technology at Booth S7546 on the 4th floor of Taipei Nangang Exhibition Center, Hall 2.

Interested in knowing how to solve the microcrack problem in through-glass via (TGV) fabrication? Interested in knowing how to supply 1,000 Watts, 1 Volt and 1,000 Amperes electricity to semiconductor IC chips in an AI multichip package? Interested in knowing how to increase the glass panel size for manufacturing AI multichip packages? If so, visit iCometrue® at Booth M0957, Hall 1, 4F, Taipei Nangang Exhibition Center during SEMICON Taiwan 2026!Benefiting from their excellent thermal, mechanical, and electrical properties, glass substrates have emerged as a promising platform for large-size, high-performance AI multichip packages. At SEMICON Taiwan 2025 last year, iCometrue® exhibited the Through-Polymer-Via (TPV) Connector, a novel technology that provides vertical interconnection in Glass Cores for use in Glass Interposers and BGA substrates to solve the microcrack problem in glass substrates caused by TGV fabrication.At SEMICON Taiwan 2026 this year, iCometrue® plans to exhibit solutions for delivering over 1,000 W and over 200 A of power supply to the high-performance AI multichip package. The solutions include:(1) Embedding Cu Blocks in Glass Substrates for Power/Ground DeliveryCu blocks are used to replace TPVs/TGVs for power/ground delivery. This approach significantly reduces the number of TPVs/TGVs originally used for power/ground delivery through the glass substrate by 80%, thereby lowering fabrication complexity, improving manufacturing yield, and reducing manufacturing costs.A current high-performance AI multichip package, comprising GPU chips and HBM modules, has more than 10,000 I/Os for power, ground, signal, and clock distribution, which requires more than 10,000 TGVs/TPVs in the glass substrate. 80% of these TGVs/TPVs in the glass substrate are used for power/ground delivery. Using Cu blocks to replace TPVs/TGVs for power/ground delivery results in an 80% reduction in the number of TPVs/TGVs, thereby lowering fabrication complexity, improving manufacturing yield, and reducing manufacturing costs. Nowadays high-performance semiconductor IC chips in AI multichip packages typically require more than 1,000 W of power. Since power (P) is given by P=I×V, a 1 V operation voltage of semiconductor IC chips corresponds to a current over 1,000 A.As shown in Fig. 1, the embedded Cu blocks provide the power/ground voltage and current paths that would otherwise require a large number of TPVs or TGVs in the glass substrate. The remaining TPVs/TGVs (approximately 20%) are reserved for signal and clock transmission. Consequently, the embedded Cu blocks significantly reduce the number of TPVs/TGVs in the glass substrate.The formation of embedded Cu blocks in glass substrates is achieved by inserting Cu blocks into pre-formed large holes in the glass substrate. This process is similar to the TPV Connector embedding process in glass substrates previously disclosed at SEMICON Taiwan 2025.(2) Packaging Voltage Converter/Regulator (VCR) chips in AI Multichip PackagesThe VCR chips are packaged vertically under and close to the GPU chip within the AI multichip package. The embedded VCR chips convert the 1,000 W, 48 V, 21 A power supply from external circuits to 1,000 W, 1 V, 1,000 A for the GPU chip. As shown in Fig. 1, copper blocks provide a low resistance power delivery system from external circuits to the embedded VCR chips, and resulting in reduction of the heat generation.(3) Embedding Si Bridges, DTCs, and VCR chips in the Frontside Interconnection Scheme Over the Glass SubstrateAt SEMICON Taiwan 2025, iCometrue® demonstrated that Si bridges and DTCs are embedded in large holes within the glass substrate. Here in Fig. 1, iCometrue® shows that Si bridges, DTCs, and VCR chips are instead embedded in the frontside interconnection scheme over the glass substrate, while the TPV connectors and copper blocks are embedded in large holes in the glass substrate. This approach further simplifies the fabrication of the AI multichip package using a glass substrate.(4) Installing Electrical/Optical Connectors at the Edges of the AI Multichip PackageWhen glass substrates are used for multichip packaging, power and signals are usually input and output via the solder balls on the bottom of the multichip package through the backside interconnection (under the glass substrate), TPVs/TGVs (in the glass substrate), and the frontside interconnection (over the glass substrate) to the semiconductor chips. As discussed above, the fabrication of TPVs/TGVs is one of the major challenges in glass-substrate technology. To solve this problem, iCometrue® has introduced an innovative architecture that enables a large-size System-on-Panel (SOP) multichip package using a thick glass substrate without TPVs/TGVs.As shown in Fig. 2, power and signals are delivered through electrical and/or optical connectors located at the edges of the multichip package rather than through solder balls on the bottom of the package. The glass substrate is used as a panel-level fabrication platform and remains in the final package to provide mechanical support. An interconnection scheme (metal line and polymer) is built on the glass substrate, with electronic components such as interconnection bridges, integrated passive devices (IPDs), and VCR chips embedded within it. Semiconductor chips (CPU, GPU, ASIC, HBM) are then flip-chip bonded onto the interconnection scheme above the glass substrate. Electrical and/or optical connectors, together with passive components, are mounted on the top surface of the interconnection scheme using surface-mount technology (SMT).Credit:iCometrueBecause power and signals are supplied by the edge connectors instead of bottom solder balls, signal transmission and power distribution from the edge connectors to semiconductor chips are through the interconnection scheme. Consequently, no TPVs or TGVs are required in the glass substrate, enabling large-size System-on-Panel (SOP) packages. Further, since no TPVs or TGVs are required, a thicker glass substrate can be used, which greatly reduces the bending of the glass panel. Thereby, the size of the glass panel used in the fabrication can be greatly increased.More than Moore: The Use of Glass Substrates for Multichip PackagingiCometrue® is pioneering a new era of advanced multichip packaging by introducing glass substrates with embedded TPV Connectors and Cu blocks, providing a practical and scalable alternative to conventional TGV-based processes. Further, embedding Si bridges, DTCs, and VCR chips in the frontside interconnection scheme over the glass substrate simplifies the fabrication of the AI multichip package. Combined with the TPV/TGV-free thick glass substrate architecture for System-on-Panel (SOP) packaging, these technologies establish a foundation for the next generation of multichip integration, extending Moore's Law into the era of glass-based system packaging and accelerating the advancem

This year's SEMICON Taiwan will be packed with discussions about artificial intelligence and the on-wafer challenges it's creating, where the advanced node and emerging technology worlds collide. And at the center of it all is the need for better process control at a reduced cost-of-ownership (CoO).Right now, manufacturers are being told to buy high-priced tools designed for the front-end advanced node world - often delivering more performance than needed at a CoO that breaks the bank. It's time to break the cycle and deliver what customers want and need at a CoO that is designed to meet the needs of their business and not simply the needs of the OEM.Enter Onto Innovation.Take control of your process and break free from costly, unnecessary platforms and patchwork solutions that prevent you from achieving truly connected process control.Here's how Onto Innovation fights the status quo and puts manufacturers in control.Advanced Node Logic: Controlling Structures at the Limits of PhysicsAt the leading edge, 3D architectures are evolving fast. Gate-all-around (GAA) nanosheets require control of individual sheet dimensions, while future complementary field-effect transistor (CFET) structures will intensify 3D metrology requirements. Both demand precise nanowire control with the data richness and enhanced signal-to-noise ratio (SNR) needed to extract more than a single dimension from a single measurement.Powered by Ai Diffract modeling software, Onto's optical critical dimension (OCD) portfolio provides the precision to identify dimensional drift in complex GAA and CFET structures. Onto's films metrology portfolio measures the ultra-thin oxide, high-k metal gate, and P/N metal stack films that make up these devices. Together, these metrology solutions help manufacturers catch process drift before it becomes a downstream issue.Advanced Memory: Keeping Pace With Vertical ScalingAs 3D DRAM and 3D NAND scale vertically and device density increases, metrology has to keep pace. Manufacturers face increasingly stringent requirements for high spectrum resolution and sensitivity, and Onto's OCD and films metrology portfolio delivers the tools to stay in control as memory scales.Silicon Photonics: Controlling a Fundamentally New Kind of DeviceSilicon photonics (SiPh) and co-packaged optics (CPO) are scaling toward broader high-volume manufacturing (HVM) adoption. These architectures can integrate laser sources, waveguide-based silicon chips, micro-lenses, and opto-electronic converters, with each introducing unique process-control challenges. Defects can show up anywhere along the optical path - in the V-grooves and micro-lens arrays that couple and align light, the waveguides that route it, the EEL/VCSEL devices that generate it, and the module-level packaging (through glass vias, bump, hybrid bonding, and reflectors) that holds it all together. Any of these defects can negatively impact yield and performance. Onto's metrology and inspection portfolio enables manufacturers to address these key touchpoints with confidence.Materials Intelligence: Control That Starts Below the SurfaceNot every problem appears as a visible defect. Charge trapping, interface states, dopant profiles, and crystalline defects can erode device performance and reliability long before a part reaches test – often beyond the reach of standard metrology recipes. Onto's materials intelligence tools are built for this layer of control: FAaST for charge and interface characterization, CnCV and QUAD for yield-critical electrical insights, Aspect S for material and structure characterization of high aspect ratio (HAR) trenches and TSV, and Celero PL for crystalline defect intelligence. With Onto, manufacturers are able to identify the variations dimensional measurements alone cannot see.Advanced Packaging: Managing Complexity Where Device Types ConvergeLogic, memory, and increasingly photonics come together in an advanced package to act as one system. Process steps like hybrid bonding, TSV, silicon thinning, and copper pad recess and dishing/topography control introduce errors that don't exist in front-end flows. Copper that protrudes or recesses even slightly at a bond interface, for example, can undermine an otherwise perfect hybrid bond; this is why hybrid bonding requires tight control of surface topography, including copper pad recess and dishing/topography, along with inspection designed to catch the sub-micron, low contrast, and non-visible defects standard inspection tools can miss. Interposers, meanwhile, introduce their own set of challenges one layer down, where measuring HAR deep trench capacitors and TSV is as demanding as it is in any 3D memory stack, and where high-speed infrared (HSIR) inspection is needed to catch defects below the surface.This need for visibility is just as important, if not more so, in an AI package. Each component in an AI package- GPU or CPU, multiple HBM stacks, an interposer, a panel substrate, and CPO - is a process control touchpoint. Onto's portfolio addresses these directly: logic OCD and film metrology for the GPU/CPU, HBM bump and RDL inspection for the memory stack, interposer inspection for the layer connecting them, panel lithography and inspection for the substrate, and SiPh/CPO module inspection wherever optics are integrated - all tied together by process control and analytics software.Dragonfly G5: One Platform for Multiple Device TypesThe Dragonfly G5 system shows what taking control across device types looks like. The system delivers sub-micron defect sensitivity down to 150nm, with best-in-class throughput across front-end, back-end, and advanced packaging applications. That versatility extends beyond traditional wafer-based manufacturing. Specialty and photonics opportunities are evaluated by application, on a single platform that handles wafers and 310×310mm panels, including glass.This unrivaled versatility is the result of several complementary inspection technologies on one platform, each one designed for a different kind of defect: brightfield and darkfield imaging for standard inspection, 3Di technology for bump metrology, a new illumination mode for sub-micron, low-contrast defects (e.g. CMP, hybrid bonding), Clearfind technology for non-visible defects, and HSIR inspection for sub-surface defects. Outfitted with TrueADC Turing machine learning classification software, the Dragonfly G5 helps manufacturers reduce nuisance defects and improve defect matching and classification accuracy.The result is a platform that follows manufacturers across device types rather than forcing them to qualify a different tool for each type. The same underlying system supports front-end and back-end inspection, advanced packaging steps like hybrid bonding and 2.5D integration, and selected specialty/photonics inspection applications.Taking Control, Device by DeviceAdvanced node logic, advanced memory, silicon photonics, advanced packaging, critical films, and AI packages feature different physics, materials, and failure modes. Onto's approach to each is the same: give manufacturers a clear, connected view of their process so problems are addressed before they become expensive.That's what taking control of your process really means - not one tool built for one device, but a portfolio designed to give manufacturers visibility and confidence across the full range of their products.SEMICON Taiwan attendees can find the Onto team at Booth L0728, September 2-4. Stop by and learn how comprehensive process control solutions can help you take control of your process, yield, and future roadmap.

DAS Environmental Expert GmbH today announced the launch of ALCEA, a new secondary abatement solution for nitrogen oxide (NOx) emissions in semiconductor manufacturing. Installed downstream of NOx-generating waste gas treatment units, ALCEA can reduce NOx by up to 95 percent while its catalyst stage is integrated directly into the exhaust duct, minimizing additional floor space in the subfab. DAS Environmental Experts will present the new system at SEMICON Taiwan 2026 from September 2 to 4 at TaiNEX 1 and 2 in Taipei (Booth J2 | 346).New plasma-enhanced catalytic secondary abatement solution integrates into exhaust ducts to minimize subfab floor space and energy demand In semiconductor fabs, additional emission-control capacity competes for limited and costly subfab space. At the same time, manufacturers are seeking to reduce utility demand, maintenance requirements, and operational interruptions. ALCEA addresses these constraints through a highly integrated architecture: the catalyst unit is fitted into the exhaust duct rather than installed as a separate floor-standing treatment stage. The solution is designed for retrofitting into existing exhaust systems and for use downstream of different NOx-generating abatement technologies. "Fabs cannot treat emissions, energy use and space as separate challenges. With ALCEA, we place a high-performance secondary DeNOx stage where it creates the most value - directly in the existing exhaust path. The result is a retrofit-ready solution that reduces NOx by up to 95 percent while keeping the demand for floor space and utilities low. That is exactly the kind of practical innovation needed on the road to an emission-free subfab", says Guy Davies, Chief Business Development Officer, DAS Environmental Experts.？？Plasma-enhanced catalysis without special gas injectionALCEA is based on DAS Environmental Experts' proven plasma-enhanced Catalytic Technology. Reactive oxygen species are formed (ROS), which drive reactions on the catalyst surface. The process converts NOx into more highly oxidized, water-soluble nitrogen compounds that can subsequently be removed in a downstream central wet abatement system. The dry-oxidation process requires no injection of special gases and the catalysts are reusable. Depending on NOx concentration, prior treatment and plasma power, ALCEA handles volume flows of up to 5,000 standard liters per minute and achieves NOx reduction of up to 95 percent. Specified power consumption is up to 3.2 kW, depending on the NOx concentration. The system supports up to two catalyst ducts for dual systems or two individual local scrubbers. Process cooling water, reusable catalysts and a design geared toward low maintenance requirements and downtime support integration into ongoing fab operations.Developed in one of the world's leading semiconductor ecosystems, ALCEA was created in collaboration with Industrial Technology Research Institute (ITRI), Taiwan's premier applied-technology research institute. The DAS Environmental Experts engineering team in Taiwan played a central role in the development.The project combines applied research, local engineering expertise and proximity to semiconductor customers. It also represents a significant expansion of the company's waste gas treatment portfolio, adding a compact post-combustion DeNOx option for new and existing fab installations. The market launch at SEMICON Taiwan underscores the role of DAS Environmental Experts' regional teams in customer-oriented innovation and local value creation. Visitors can learn more about ALCEA and the company's wider portfolio for waste gas and wastewater treatment during SEMICON Taiwan 2026. For more information, please visit DAS Official Website and product detail page. 

At SEMICON Taiwan 2026 Booth T9116, SiliconAuto will showcase automotive-grade silicon solutions for Physical AI, developed through collaboration across Taiwan's world-leading semiconductor ecosystem. Visitors can experience live demonstrations of technologies designed to power future robotics and autonomous driving applications. The solutions are built on the XMotiv M3 microcontroller and high-performance computing (HPC) platforms used in intelligent vehicles and robots.Throughout the exhibition, the SiliconAuto team will be on hand to discuss practical approaches to Physical AI development. Topics range from semiconductor architecture and system design to multi-die integration and packaging. Visitors can also get hands-on with XMotiv M3 developer kits for robotic motion control, automotive body control, and safety orchestration.Automotive-Grade Silicon, Purpose-Built for Safe and Secure Physical AIExperience SiliconAuto technologies in action through three demonstrations, spanning robotics, autonomous driving, and high-performance computing. First of all, the XMotiv M3 as an ASIL-B Robotics Controller. In collaboration with Nexuni, a Taiwanese robotics developer focused on bringing AI-powered robots into practical, everyday applications, SiliconAuto is debuting a robotic motion control developer kit. XMotiv M3 controls dynamic stabilization through joint actuators. The demonstration highlights XMotiv M3's high-speed interface capabilities. These capabilities enable real-time control. ASIL-B compliance lays the safety and security foundation.Secondly, XMotiv M3 for Autonomous Driving. See how MCU XMotiv M3 works alongside ZF's I/O interface chip to support autonomous driving capabilities up to Level 4. This autonomous driving solution was first unveiled at Embedded World 2026 where it received the Embedded Award in the SoC/IP/IC Design category. The solution demonstrates XMotiv M3 performing safety orchestration, including system management and security functions.Moreover, the Physical AI Multi-Chiplet System. Get an exclusive preview of SiliconAuto's next-generation Physical AI inference solution. The solution is built on an automotive-grade high-performance computing (HPC) chiplet architecture, designed to meet the demanding requirements of future autonomous vehicles and advanced robotics platforms. The demonstration is powered by the SiliconPilot digital twin, which provides a pre-silicon model for validation and development.As Physical AI drives the emergence of autonomous vehicles and robots, SiliconAuto is helping customers bridge the gap between AI thinking and physical action. Through automotive-grade silicon solutions, built on XMotiv M3 microcontroller, high-performance computing (HPC) platforms, vehicle-to-everything connectivity solutions, and collaboration across Taiwan's world-leading semiconductor ecosystem, the company is enabling the next generation of safe and secure Physical AI systems. To know more about SiliconAuto, please visit during SEMICON Taiwan at Booth T9116, Level 7, TaiNEX Hall 2 or visit offcial webiste. 

Rapid evolution of High-Performance Computing (HPC) and artificial intelligence chips for Hyperscalers and tech giants continue pushing large sized silicon demands. As a core element of semiconductor value creation, advanced packaging technology is scaling the stacking of more computing cores, more high-bandwidth memory, as well as the adoption of modular chiplet integration to overcome physical boundaries. Leading semiconductor manufacturers are expanding package dimensions to unprecedented footprints, currently reaching sizes of 100, 120, with projections moving beyond 180 mm to support large-format AI-driven advanced packages.The semiconductor industry is responding and shifting toward solutions that combine large-scale mass production with large-format packaging capabilities. Square sized substrates offer a distinct area utilization advantage to accommodate more large-form-factor chips simultaneously by moving away from round wafers to large rectangular panels. This is improving cost efficiency and addressing the challenges of thermal warpage and high-density interconnects associated with massive AI packages.Glass substrates are emerging as a key technology for advancing panel-level packaging from pilot experiments to active equipment qualification and commercialization verification. Consequently, Redistribution Layer (RDL) wet process and ECD equipment has become a critical driver of this transition and a key step in glass substrate manu-facturing. Key production tools including Electrochemical Deposition (ECD), cleaning, developing, etching, and stripping are not only vital to glass core substrate manufacturing, but also central to achieving high yields and mass production capabilities in advanced packaging technologies such as fan-out panel-level packaging (FOPLP) and Chip-on-Panel-on-Substrate (CoPoS). The wet processing equipment has garnered significant market attention.Omni production platform supports cross-sized substrates in 310, 510 and 700mm panelManz Asia, has successfully delivered Omni 310 system, which is the world’s first $310\text{mm} \times 310\text{mm}$ ECD wet chemistry system in early 2026. The system uses an electrochemical deposition module as its core, combining wet processing tools including cleaning, developing, plating, etching, stripping, and dual mechanisms support for both spin and spray operation. This new platform addresses the adaption to varying rectangular substrates.At SEMICON Taiwan 2026, Manz Asia expanded its portfolio with the launch of the cross-sized Omni series production systems. Engineered for varying panel dimensions, packaging architectures, and strict process requirements, this series feature the Omni 310, Omni 510, and Omni 700 to deliver optimized panel-level packaging (PLP) solutions across 310mm, 510mm, and 700mm panel sizes to meet the requirements of advanced PLP technology roadmaps including FOPLP, CoPoS, and Glass core TGV manufacturing.Take early-move positioning for Glass Core substrate aiming to tackle Through-Glass Via challengesRapid advancements in CoPoS are driving the shift from organic substrates to Glass Core, with TGV metallization, seed-layer formation, and copper via filling emerging as key process challenges. The Omni Series RDL platform integrates glass surface modification, cleaning, electroless copper plating, and electroplating to enhance copper adhesion and enable reliable TGV metallization and filling. Major Benefits of Omni series include.High performance ECD technology: The system offers excellent capabilities for filling high-aspect-ratio through-vias. When combined with an optimized seed layer and specialized plating chemistry, this process enables void-free via filling, delivering a highly stable and critical solution for electroplating on glass carrier substrates.High-precision glass etching technology: Featuring robust glass micro-machining capabilities, this technology supports the processing of 0.4 mm glass substrates and the creation of $20\ \mu\text{m}$ micro-vias. It offers TGV process capabilities with aspect ratios of up to 1:20, providing a critical advantage for achieving deep, fine-featured vias. Therefore, the system addresses the challenges of high-density TGV designs and marks a milestone in establishing a mass-production platform for next-generation packaging architectures.Empowering Heterogeneous Integration with advanced RDL for High-Precision Multi-Layer InterconnectionWith 40 years of in-house R&D expertise in RDL processing, Manz Asia has developed extensive expertise across PCB, IC substrate, display panel, and semiconductor packaging applications, and is now building strong collaborations with global IDM and OSAT clients. By helping customers accelerate key process iterations and transition smoothly to mass production, Manz Asia plays an active role in the global RDL processing and panel-level packaging supply chain.Designed for next-generation advanced packaging technologies like CoPoS, FOPLP, and Glass Core TGV, the debut of the Omni series production systems helps customers accelerate their transition from R&D validation to mass production. To learn more about Manz Asia production systems and product offerings, please visit the booth M1248, 4th Floor, Hall 1, Nangang Exhibition Center at SEMICON Taiwan 2026. You can also view detail product information on the official website.