Entegris, Inc. (NASDAQ: ENTG), a leader in yield-enhancing materials and solutions announced today the release of Torrento X Series 7 nm filters with FlowPlane linear filtration technology. FlowPlane is the semiconductor industry's first scalable, linear, high-flow filtration platform enabling advanced wet cleaning applications for the 10 nm node and beyond. The first in a series of filters based on the linear filtration technology, the FlowPlane S model is designed for point of dispense (POD) applications, enabling improvements in both on-wafer defectivity and yield for critical wet cleaning applications."We've reached an inflection point where filter design must evolve to meet the needs of the most complex semiconductor manufacturing processes," said Entegris Vice-President of the Liquid Microcontamination Control business unit, Clint Haris. "A filter is the last line of defense to prevent defect-causing contaminants from reaching the wafer. Our smaller, more powerful filtration solution will enable our customers to effectively implement their 10 and 7 nm technology nodes."Torrento X series 7 nm filters with FlowPlane linear filtration technology improves retention and increase flow rate performance by 100% compared to similarly sized radial filters. Moreover, FlowPlane users will benefit from the format's smaller device footprint as well as improved wafer defectivity performance.For more information about the Torrento X Series 7 nm filters with FlowPlane linear filtration technology, go to http://www.entegris.com/.FlowPlane linear filtration technology with Torrento X series 7 nm filters improves retention and increase flow rate performance.

Driven by the consumer IC market of emerging applications, such as CMOS Image Sensor (CIS), and 8-bit or 16-bit MCU for the controller of Internet of Things (IoT) in Health Care, Smart Energy System or Intelligent Family field, various product types, reference design and development tools and R&D staff training are needed to provide. To response to the prompt demand, the designers need rapid construction structures to come out new cells in a short time and less or even no trainings for new users, an open environment which can be integrated with third party tools to facilitate all design flow and a custom solution to optimize the layout.Thus, the IC layout designers need a unified, simple but powerful layout solution to design PCell, run simulation, debug and verify in the same environment to deliver time-to-market and high quality products. GOLF is a Schematic-Driven and OpenAccess-based layout solution that provides the full hierarchical manipulation capability to increase layout productivity up to a maximum of 30X+. GOLF provides a complete solution to design and debug PCell, run 3rd party DRC, LVS or LPE tools and generate test key in an integrated development environment (IDE).Benefits- Schematic-Driven Layout (SDL) provides the efficiency of debugging, high layout productivity in an easy-to-use environment- GUI-based, rich PCell primitive types and parameterized IDE environment to convenience the layout design and reduce the learning curve for new users- Test Key Layout Generation reduces product time-to-market by guided and parameterized test structures, automated and efficient methodology. - GOLF's custom layout service completes your layout solution and can increase 10X+~30X+ productivity.Open environment and extensible architectureGOLF is an OpenAccess-based layout solution that provides full hierarchical manipulation capability to increase layout productivity up to a maximum of 30X+. GOLF provides comprehensive methodologies which include powerful layout editing and debugging functions, intuitive GUI, flexible customization and extension with TCL/Perl/Python/C++ to enable layout designers to achieve correct-by-construction results.Intuitively design PCell with parameters in GUIGOLF provides PCell design, preview, testing, debugging, and documentation in a unified environment. Designing Cell in GOLF is parameterized and step-by-step; just entering parameters for a PCell in GUI instead of programming codes, even the engineers without any programming experience can follow the steps to come out PCells directly. It is based on Anaglobe's patented highly flexible and reusable hierarchical parameterized layout generator.More than the types that system-predefined, over 40 primitive PCell objects are provided to ease the use of devices and various operators are also supplied for the convenience of device modification or reuse. Special shapes also can be created easily in GUI as well.Intelligent test key layout generationTest key layout generator is the solution for test vehicle development by creating reusable and parameterized test structure. Designers only need to input parameters, define split table with or without routing constrains, then the test module can be interactively generated and assembled to place test modules into a single top design. With this solution, the conventional test chip development flow can be changed into an efficient, consistent and automated methodology.Schematic-Driven layout solutionAnaglobe's GOLF is the worldwide proven layout solution which enabling users to overcome the challenges of today's demand from the volatile market with little or no learning curve. Schematic-based editing and step-by-step guided layout tasks are just accomplished with easy clicks, parameter inputs or intuitive menu accesses.SDL operates with a hierarchical connectivity model working simultaneously at all levels of the design hierarchy. This capability will alarm connectivity errors as the net is short or open. This makes designers easier to understand the complexity of interactions through the design hierarchy.SDL also supports one-to-many mapping across multiple hierarchy levels. This allows layout designers to view different layout hierarchies at the same time for efficient net tracing or debugging. The cross probing of hierarchy net tracer and short Indicator can easily highlight the problem net without Place-and- Route (P&R), LVS or LPE. It does significantly reduce efforts and speed up the debugging processes.Custom layout solutionThere is always the gap between the solution of the standard layout tool and problems that users have. With GOLF's customization service, complete layout requirements can be satisfied and productivity can be increased up to 10X+~30X+. One example is to unify the test chip layout with customized P&R and parser in GOLF only that you don't need to switch in various tools, spend time in database transformation any more. There are also other reference customization projects as described below:- Dummy pattern insertion- Net checker- Bump cell placer- Web-based analysis and inquiry system - Customized tape-out flow- Defect inspection flowJoin GOLF customization, then you can spend less and get more.ConclusionTo shorten the layout cycle and maximize the productivity, GOLF – provided by AnaGlobe (http://www.anaglobe.com/), does address the problems that deep nanometer layouts meet and provides the highly integrated, multi-vendor tool suite for custom and cell-based design and verification .The leading-edge semiconductor foundries or famous design companies do gain from the adoption of GOLF to layout their analog, mixed-signal, logic, embedded memory or RF designs.Open environment and extensible architecture

Wireless communication technologies play a critical role in the rapid rise of mobile devices. Multi-band configurations have particularly contributed to the launch of 4G smartphones. A general 4G phone for use around the world is expected to support over 40 frequency bands in 2016. To keep up with advancement of the highly complicated technologies, it is essential that IC developers and RF module system assemblers with ambitions to grab a share of the market overcome the technical barriers of RF FrontEnd( RFFE) testing as phone signal reception quality and energy consumption are both closely related to the control of PA characterization.IC design teams have to do additional testing required by signal processing with respect to the PA specs they need to follow. Items including dynamic EVM, ACLR, PAE and RF output power, DC power supply, and channel frequency have to be individually scanned and tested to confirm if the performance of the product that has been designed meets the standard. As IC validation is more challenging than system module testing, IC test engineering teams generally work under tremendous pressure and have to race against time on a daily basis.IC testing generally starts from setting up various testing instruments and machinery, generally including oscilloscope, spectrum analyzer, a few signal generators that can simulate PA-enabled signals, power supplies needed to simulate PA power sources and a variety of measuring equipment. To model a test environment with fixed conditions, operators generally have to use GPIB to connect all the equipment. The preparation work alone is a daily struggle with all the wire connections behind the instruments.Operators can then perform measuring, logging and analyzing, and the data is compiled in an Excel file and turned into graphs and charts which are used to verify against IC design specs to check for incompliances or errors. With every design modification, the entire testing process has to be repeated again. It may take a novice team weeks or even months to master the overall process. Therefore, it is natural for product managers and engineering project leaders to feel concerned.LitePoint has delivered comprehensive automated testing solutions for production in mass quantities, helping manufacturers deliver billions of smartphones to the market every year. Realizing that the extremely demanding testing and verification work in a laboratory can no longer be carried out in the way that it was done before, LitePoint offers zSeries' PA/FEM total design validation solution for optimized testing of PA and FEM modules used in mobile devices.Because of LitePoint's long-term collaboration with mainstream PA chip makers, LitePoint is able to offer zSeries with a complete understanding of PA characterization and a modularized hardware design integrating all the measuring instruments needed to perform testing in a rack mount chassis with 9 or 18 slots for insertion of the hardware modules. zSeries' design frees test engineering teams from complex wire connections so that they can focus on the demanding function verification work.In addition to flexible hardware configurations, zSeries also provides software support by using a language architecture similar to a test script to enable editing and modification of different configuration profiles which are similar to regular .BAT files that engineers are familiar with. The scripting language is well liked as some test engineers of LitePoint's customers have nicknamed it "LitePoint Language."When repeatedly testing PA characterization, test engineers generally have to process a great amount of test data so LitePoint offers IQramp, a data analysis system that makes use of Big Data Analytics and automatically generates reports and charts in PDF format, to help with validation work. Therefore, zSeries is not just a simple tester but a complete solution integrating software, hardware, Big Data analytics, and report creation tools. As Shawn Knapp, LitePoint's product application manager, points out, zSeries not only accelerates the testing process but also offers a flexibly integrated automated testing platform for validation applications in laboratories and during the IC or module manufacturing process. It gives IC designers and RF module makers a flexible approach to enhancing product quality.zSeries impresses Japan market with promising expansion to other Asian countries for its precisionA case about a LitePoint customer using zSeries is worth mentioning. When a system assembler used zSeries to test the PA characterization of an RF module made by an RF module vendor with its internally-developed PA chip, the system assembler was able to discover that the dynamic EVM did not comply with the specs. This was a problem that the original PA design/test team failed to catch in the lab and was found and solved because the system assembler used zSeries, enabling high-precision testing that impressed the Japan industry.With zSeries, system manufacturers can learn about PA characterization and thereby gain knowledge on new technologies including dynamic EVM, Digital Pre-Distortion(DPD), and Envelope Tracking(ET), which will help improve their RF IC design capabilities. The testing and verification processes enabled by zSeries will boost overall quality and enhance differentiating features of next generation RF IC designs and applications. For engineering teams that design systems integrating baseband, power management, application processors, and RF modules, competition is escalating and wireless transmission technologies are advancing by leaps and bounds. But zSeries, with robust function verification and automated testing capabilities, will help IC designers and RF module makers achieve their goals of time-to-market efficiency.zSeries provides tools to generate test data graphs and charts in addition to a Big Data analytics system to enable PA and RF FEM testing

Both OEM and brand-name electronics manufacturers trying to shorten time-to-market have to develop capabilities to expedite time-to-production so that they can maintain an edge over competitors by being able to make products in mass quantities, with high yields, and at continuingly reduced costs for a chance to win market support. This applies to manufacturing of all sorts of products and also to the emerging IoT industry where products feature low volume and high mix with constant challenges on testing technologies.How to find the best solution to product testing is an industry-wide challenge. LitePoint endeavors to help Taiwan-based manufacturers in the search for innovative thinking on testing technologies and offers complete solutions by convening a forum every six months.The 2015 LitePoint forum featured two sessions on July 21 and 23 respectively in Hsinchu and Taipei, both of which centered on how LitePoint wireless testing technologies can be used to raise efficiency of testing during production and function verification during product design, and to offer complete testing solutions targeting emerging IoT trends. To propose an ideal testing solution, LitePoint started the forum with the message, "What is the value of testing?" presented by Adam Smith.The real meaning behind testing is the pursuit for product qualityIn his presentation, Adam Smith, Director of Product Marketing at LitePoint, started out by outlining the importance of testing as it ensures product quality. A product without quality has neither market opportunity nor a chance at succeeding, regardless of whether it is a master design, ingenious creation, or monumental work.Wireless transmission technologies are advancing by leaps and bounds. Take a 4G smartphone for example. The product design has to take into consideration the number of frequency bands likely to grow from five to over 20 by next year and additional support for two to three wireless transmission standards including WiFi and Bluetooth, requiring a total of eight antennas in general. Moreover, 30% of new phones on the market next year are expected to come with dual SIM card support so the testing items will also have to include WCDMA and GSM. It will definitely take a tremendous part of production time to test products integrating all these complicated functionalities on a small device, covering transmission over all the wireless channels, and supporting different chipset modules. This will result in an increase to production costs and therefore impact profitability. The situation calls for a provider that is capable of delivering total integrated testing systems and production solutions.Similar to the case of handsets, testing for WiFi devices is also very challenging. Additional antenna testing conditions are required for the 802.11ac Wave 2 standard with MU-MIMO and Beamforming. Furthermore, WiFi transmission in competition with LTE for the 5GHz frequency is error prone, so testing is essential to ensuring product quality and thereby upholding brand reputation.DUT Sense, Fixture Health Check, and APLC help build up production lines and enhance overall testing efficiencyToday we see over 1 billion smartphones manufactured on the production line every year and each one has more antennas that need to be tested and verified on different testers. As such, it is natural that manufacturers are very calculating about the time required to do the testing and also the space needed to set up the testers, the arrangement of the jigs and operation dynamics.Through continuing communication and work with customers, LitePoint has developed a set of new tools that help customers improve their testing station configurations including equipment, wiring, and jig check. Before complicated DUT goes on the line, software tools including DUT Sense that performs calibration, Fixture Health Check that checks jigs and probes, Automatic Path Loss Calibration(APLC) that examines cabling and connection efficiency assist customers with the essential preparation for setting up a testing station on a production line.zSeries meets challenges regarding function verification and manufacturing for chip designers and system assemblersA mobile phone's user experience is determined by its performance with respect to signal reception and power efficiency, which is related to the RF FrontEnd(RFFE) design. A general 4G phone for use around the globe has to comply with a variety of 4G transmission specs in different countries and support over 40 frequency bands. With the 5GHz frequency soon to join the competition, chip developers are struggling with challenges arising from the complexity of multi-mode multi-band testing and therefore are in need of help from providers of RF modules. Testing tools that can facilitate IC design houses to verify functions of their chips or enable system assemblers to test RF modules become very valuable.The PA/FEM solution provided by LitePoint zSeries focuses on testing of power amplifiers and RFFE modules. In addition to different chip specs used in RF FEM modules, additional verifications required by signal processing, such as dynamic EVM, ACLR, PAE, RF output power, DC power supply, and channel frequency, are also scanned and tested. Furthermore, special verification processes including Digital Pre-Distortion(DPD) and Envelope Tracking(ET) needed during design are also incorporated. LitePoint's product application manager for zSeries stresses that the consideration about testing not only encompasses accelerating the verification process but also ensuring the end product performance matches brand reputation on quality. This can be achieved by zSeries that delivers a flexible combination of automatic testing platforms satisfying requirements by both design verification and manufacturing applications.Innovative IoT applications inspire new testing thinkingInnovative applications and new startups are flourishing with booming IoT developments and are attracting attention from consumers and investors. However, IoT is still at a stage where a multitude of companies are competing against each other and the key to winning lies in the user experience and product design as well as aesthetics. From a technological perspective, under the surface is a contention among a host of wireless transmission technologies, Big Data analytics, and software platforms provided by tech alliances and group leaders. Therefore, we will likely see integrated technologies continue to emerge.LitePoint's presentation showed a series of wireless technologies that are likely to be integrated, including BT4.2, WiFi, ZigBee, WiSUN, Z-wave, NFC, and LTE Cat0, each with its own advantage. It is still unclear which wireless technology will become dominant. WiFi and related standards are promising as they are widely used but power consumption remains an issue. New WiFi 802.11ah spec attempts to reduce power consumption but is still at draft stage. BTLE, ZigBee, WiSUN, and Z-wave have an advantage in terms of power efficiency but data transmission rate needs improvement. NFC is most special in that it is more like an inductor coil of a transformer than a wireless protocol. However, its security feature surpasses all the others so people highly anticipate the technology but it is still unclear if NFC will stand out and become dominant.LitePoint's product manager raised as many as four questions at a time about IoT device testing. Can you make money only by cutting corners? Does testing necessarily cost you an arm and a leg? Is RF testing undoubtedly difficult? Is it enough to do simple Go/NG DUT testing? Everyone may have different answers to these questions. However, LitePoint solutions will definitely offer you a more positive answer for your IoT device testing.Evolution of 802.11ac Wave2 and new challenges in testing VHT 160, 1024QAM, and BeamformingMainstream chip vendors providing 802.11ac Wave2 chips remain a minority as the market development is still at infancy. However, LitePoint is closely watching the trend to help customers create differentiating product features and capture new opportunities. Beamforming uses constructive interference generated by signals from multiple antennas and concentrates beams in the direction of the client device. Signal coverage in the direction of the client device can be increased to help WiFi AP signals penetrate through walls. Beamforming comprises Explicit and Implicit Beamforming based on the spec. Implicit Beamforming (IBF) assumes downlink and uplink channels have the same conditions and only uses uplink signals for channel estimation, which is then used for downlink signal compensation. However, such an assumption does not work in the real environment so Explicit Beamforming (EBF), dynamically performing channel estimation on both uplink and downlink channels and then making signal compensation, is developed to achieve better beamforming effects.Beamforming is very sensitive with respect to phases. PCB using different components for receiving and transmitting circuits will result in phase differences in uplink and downlink signals so production of devices with the beamforming technology requires beamforming calibration to ensure the differences will not affect beamforming performance. Furthermore, special care has to be taken regarding different beamforming calibration algorithms used in chips from various vendors. LitePoint IQxel-M8 can adjust to different chip vendors' beamforming calibration methods, thereby giving considerations to a variety of testing requirements.LitePoint's IQxel-160 and IQxel-M16 solutions additionally cover testing for some new technologies not included in 802.11ac, such as 1024QAM. In particular, IQxel-160 has become a standard tester for almost all mainstream chip developers attributing to LitePoint's long-term cooperation with chip makers, which in turn benefits other LitePoint customers as well.Adam Smith, Director of Product Marketing at LitePoint, presenting views on technology trends and values of wireless testing at the forum

From the prompt demands of semiconductor, the killer applications are handheld devices, wearable devices, automotive applications and the Internet of Things(IoT). Most ICs are manufactured beyond 65nm and even more advanced processes. Such a SoC may include multi-core CPU, application processors, communication IPs such as Wi-Fi, Bluetooth, 3G or LTE and multi-type of sensors.Layout ChallengesSuch rapid increase of chip complexity results in the revolution of layout design. Not only the functionality and quality of a reliable product must be ensured, but also many ultra deep submicron (UDSM) effects can no longer be ignored any more. The understanding of analysis or simulation alone is not showing enough value. The future trend is the layout tool can have the capability of the intelligence beyond the ability of ordinary people to know how to judge and decision-making.Thus, the layout engine must be powerful enough to produce high-quality layouts. This includes respect for the design requirements such as large scale layout size up to several hundred GB, debugging capabilities with clear and smart net tracing, critical area analysis and density control, edge effect analysis and pattern analyzer of big data of wafer map. All the layout requirements must be fulfilled in a unified, friendly and hyper performance environment to deliver high yield and time-to-market layouts.A Complete Solution with ThunderTo overcome the layout challenges, Thunder provides an intelligent and a complete layout solution which has Hybrid Design Database (DDB) and Defect Knowledge Database(DKDB) with data mining technologies, accelerator, optimizer and analysis engines. The technologies are Big Data Analyzer for defect analysis, Performance Accelerator for large layout size and performance issues, Dummy Fill Optimizer for non-uniform density issues, and De-duplicated Merge to reduce the file size of the redundant cells when performing IP merge. With these technologies, Thunder can handle design capacity up to 500GB+ and provide the full SoC manipulation abilities with industry-leading performance.Early Warning of Potential Defects with Big Data AnalyzerTo dig out the potential wafer defects, Thunder provides a powerful mechanism to automatically identify the defect signatures from KLARF. Thunder contains a Defect Knowledge Database (DKDB) and a robust Big Data Analyzer that can automatically compare the design data in DDB to the defect signatures in DKDB to know whether the wafer with the defect patterns or not . With Defect Extraction technology, engineers can visualize in a more trivial way ; the Big Data Analysis Engine allow the defect engineers to generate and manage their own pattern library and set the threshold to notify them when the results of Statistical Monitor exceed the threshold. This engine is also helpful for engineers to optimize parameter settings or fine tune the analysis sequence to gain the better improvement of yield.Hyper Performance Import for High Capacity Design with Direct Import TechnologyMost layout tools save the layout to the disk when importing it at the first time. Anaglobe's professional designers find that saving layout designs to disk when importing does result in the performance bottleneck and even the hanging process sometimes. To break through the bottleneck, Thunder saves and runs it in the main memory directly instead of saving it back to the disk when layout files are imported. With the direct import technology, the layout size that Thunder can import is over 500GB+ which is the biggest one over all current layout tools!LVL Performance Accelerator with Layout Analysis EngineInstead of comparing each layout one by one for LVL comparison, Thunder provides the fastest performance of LVL comparison, linear to data size, to quickly identify the differences between two designs. The intelligent layout analysis engine has the ability to quickly differentiate whether two blocks are possible to be the same or not. When they are not, further detail comparison will be no longer processed.Uniform Layout Density Distribution with Dummy Fill OptimizerNon-uniform density will degrade analog circuit performance and impact the yield. It needs intelligent methodology to check the critical area and generate the dummy cells accordingly. Thunder provides a density map generation, violation checking and rule based dummy metal fill insertion to resolve the density issue completely. Beyond other tools, small region can be done as well. For dummy fill insertion, it can insert a uniform and regular metal pattern to low density area according to the target percentage interactively and creates vertical or horizontal patterns with offset.Comprehensive Debugging with 3D VisualizationThunder's powerful 3D net tracer provides both tracing and highlight problematic nets with 3D visualization. It supports both location based and pin text based tracing. 3D View is not only for net, but also for finFET or Cut Layers.Consolidate IP Merge with De-duplicated Merge TechnologyWhen merging IPs, Thunder has a very smart mechanism, De-duplicated Merge Technology, to detect and remove the redundant layouts of cells. The power of De-duplicated Technology is to use LVL comparison during the merging process to know whether the layouts of the cells are exactly the same or not. When they are the same, only one layout will be kept in the design and other cells will be renamed. That's the way for Thunder to consolidate the design. The merge results are also very impressive to the layout designers. The best case is 60% GDS size can be saved!ConclusionWorking in Thunder's environment allows you to start from the layout prototyping, IP merge and yield improvement in one unified platform. Intuitive GUI and 3D layout view enables the efficiency of debugging. Thunder also can communicate with the third party tools and provide big data analysis for wafer inspection results. Uniform layout density distribution and dummy fill insertion in critical area also can be done automatically and intelligently. In short, Thunder is a total and an optimized customization layout solution which does address to resolve all deep submicron layout issues and can increase 30X+~50X+ productivity! Thunder – provided by AnaGlobe (http://www.anaglobe.com)A complete solution with ThunderEarly warning of potential defects with Big Data Analyzer

Who today doesn't think IoT is cool? And, why not? We're in an era where everything is connected to everything else in a six degrees of separation-like scenario for our electronics devices.Smart homes, smart autos and even smart cities are all cool amenities to make life easier and more comfortable. Smart, wearable consumer devices, such as running shoes and fitness trackers, furnish us with a personal health coach on our feet or wrist. Smart health and wellness applications are popping up everywhere, giving anyone with a smart phone or tablet instant access to an informed medical professional. Smart tile, a Bluetooth tracker, helps find lost or misplaced keys or wallets. A smart button creates shortcuts to our phones. Automatic washing machines and domestic refrigerators were cool to our grandparents because they enabled them to have more time for other pursuits. IoT is cool today for the same reason.Much of this innovation is due to a common hardware platform that has enabled what will be close to 50-billion connected devices by 2020 and lets consumers access multiple time-saving, health-conscious applications. In these new devices, the differentiation is created in embedded software, not so much hardware any longer. The embedded memory requirements are stringent and range from a small silicon footprint and low power with instant-on to programmable, non-volatile code storage. Most important is a guarantee that the memory is highly secure to protect software IP and prevent hacking of these next-generation devices.The need for high secure memory and lower power memory is greater than ever because that is what's needed for the coming devices that could make us better than what is humanly possible. Today, connectivity is ubiquitous. Sensors are ubiquitous. Hardware cost is decreasing because of Moore's Law. We love to share (or don't know we are sharing) through various social media platforms or application services. Next-generation smart peripherals could address improving our five senses: sight, taste, smell, touch, and hearing.As we age, our hearing gets worse. Smart phones now have a microphone that can capture the ambient. What if the phone or another form factor in the future could hear better than we do and alert us of the environment around us or of possible danger? We can have context awareness, which will allow us to be aware and perhaps anticipate. We have just started to think about what is possible with IoT and, maybe, not thinking big enough about the possible applications.Winners of this emerging IoT market segment will be devices featuring low power and hack-proof security. They will be inexpensive because the hardware will be tightly coupled with differentiating embedded software. And, naturally, they will have multiple application services onboard. Today, we trade data unknowingly, and the need for security will continue to be important.Power, power and more power will become even more important when we think about the changing mankind type of applications. We can't have a lithium battery in our eye when there's a contact lens helping us see beyond 20/20. Bitcell current of embedded NVM needs to be reduced in addition to the traditional peripherals done today.From the cool applications of today to the life changing peripheral applications of tomorrow, the technology requirements are advancing, and the NVM technology used for these applications needs to be at ultra-low power, low cost, and highly secure. It will be exciting to see, with these accomplishments, what the next generation applications can do for humankind.For more information about Kilopass Technology, please visit: http://www.kilopass.com/

Leading semiconductor test equipment supplier Advantest Corporation's (TSE: 6857, NYSE: ATE) subsidiary Advantest (Singapore) Pte. Ltd., outsourced semiconductor assembly and test (OSAT) foundry Fabtronic Sdn Bhd and Malaysia's Northern Corridor Implementation Authority (NCIA) have entered a strategic partnership to enhance the test-development and product-characterization skills of IC test engineers by establishing a laboratory and professional training center in Malaysia's Northern Corridor Economic Region (NCER). The partner organizations expect the program to help reduce development costs and improve time to market for semiconductor devices made in Malaysia.The three organizations signed a memorandum of understanding (MOU) to jointly launch a shared-services test laboratory and skills development training program at the Northern Corridor Technology Development Center (NTDC), located in Phase 4 of the Bayan Lepas Free Industrial Zone in Penang, Malaysia. The new lab and training program will be run by Fabtronic, which has equipped the facility with a V93000 Smart Scale test platform from Advantest. This scalable system is designed to support both engineering and high-volume manufacturing applications."We enthusiastically support this cooperative venture to grow Malaysia's high-tech ecosystem, expand its skilled labor force and improve product-development efficiencies," said Paul Lau, managing director and CEO of Advantest (Singapore) Pte. Ltd. "Advantest is proud to be a founding member of this three-pronged coalition of private-sector and government groups helping to bring the first shared-services test lab to Southeast Asia."More information about Advantest Corporation is available at http://www.advantest.com/.

Undoubtedly, the hottest topic currently in the manufacturing sector is "Industry 4.0," and most firms hope to utilize ICT, software and Internet of Things (IoT) technologies to build up their smart and automation synergy. However, everything has a beginning. To enter Industry 4.0, firms need to have a strong automation foundation, and through data collection and analytics, smart decisions can be made.Industry 3.0 saw the industry utilize computer technology to turn hardware control circuit into software, and make it more digitalized. Industry 3.0 gave birth to PLC supporting complicated logic. This was a huge improvement compared to Industry 2.0. And now, as we move towards Industry 4.0, the goal is to use the bases we have now and integrate elements such as cloud computing, big data, and IoT technologies. Smart processes can help the industry shorten the time needed to complete the otherwise tedious and time-consuming operations such as manufacturing process management, procurement, and production scheduling. And such a prospect alone is already enough to whip up much interest in Industry 4.0 among firms.Wen-Jinn Liang, vice president of Toes Opto-Mechatronics, a subsidiary of Tatung Company, notes that the advantage of Industry 4.0 is not limited to just reducing labor cost, as it also brings more added values. For example, Germany has been eager to promote the cyber physical system (CPS) integration concept which allows firms to use 3D virtual software, motion simulation robots, modules, and other equipment to detect design flaws and interferences. This allows them to preemptively repair weaknesses and increase design efficiency. This is a huge step to shortening the time-to-market process.Moving towards smart manufacturing requires strong foundation for automationSo how do firms build a smart manufacturing environment that is in line with the spirit of Industry 4.0? Liang believes there are two key foundations – the smart factory equipment maintenance system and automated precision assembly. In particular, automation is the necessary key. To achieve automation, firms need to plan an effective production line and continue to promote smooth workflow and standardization. If there is anything amiss in the preparation, automation may fail easily, resulting in setbacks on the road to Industry 4.0. With nearly 40 years of automation experience under its belt, Toes can help firms with the overall planning, laying a strong foundation for automation.To allocate the production line with efficiency, the layout of equipment must be carefully considered to prevent badly designed flow that could undermine efficiency in the future. Secondly, a smooth workflow needs to be based on the principle of "line balance," and extra workstations may be needed or flow may have to be diversified according to the bottleneck at each workstation. This can reduce an unnecessary waste of work hours. Standardization can be divided into two categories: procedure standardization and component standardization. The former can avoid negative effects on utilization rates while the latter can prevent equipment malfunction from lowering yields.When these basics are completed, the next step is to utilize robots, visual control and sensors to move towards the smart automated process. However, many firms who are interested have been deterred by a lack of return on investment (ROI) after evaluating the costs. For example, a firm may spend millions of dollars procuring a robotic arm, only to use it in simple procedures such as picking up and putting down parts. Meanwhile the idle time of the robotic arm is also higher than expected.Liang believes that to achieve smart automation, firms do not need to spend a lot of money. For example, production lines can use low-cost sensors and motion control systems; and with the help of feature recognition technology for working parts they can smartly achieve smart automation with reasonable ROI to quickly fulfill customers' needs for products of different colors, materials, and types.Automation combined with software analytics to form Industry 4.0 value chainSome production lines cannot add extra process steps to handle the entire production process due to a lack of space. This means no matter where the robot is placed, it may only be able to do simple jobs and the true value of this investment will be hidden.Addressing this type of problem, Toes utilizes the robots' characteristics of flexibility to come up with the idea of placing the conveyer to next work station above the physical space of the robot. With a specially-designed multi-functional claw, the robot can handle multiple tasks such as applying grease and baking at the same time. Once the baking process is completed, the robot can place the product onto the conveyer above its physical space for further processing. This is a creative idea.Liang says that if we imagine Industry 4.0 as a person, the smart automated movable parts of the equipment are like the arms and legs; the real intelligence comes from data collection and analytics, which may even have to rely on professional systems or algorithms to make smart decisions.Hence Toes assumes the role of providing smart automated SI solutions, which facilitate utilization rate or quality analysis based on data obtained from the equipment and sent to MES through the CIM interface. The data can further be used for cost analysis in the ERP system. At last, with cloud computing and big data analytics, the data can help firms make smart decisions to achieve the goal of both maximizing the volume of orders and efficiency, and minimizing cost.The value-added services Toes offers have begun to bloom in Taiwan and China. For example, with Toes' help, a China-based traditional manufacturer has reduced the number of labor by nine units per production line while increasing capacity by three-fold. The efficiency is astounding.Wen-Jinn Liang, vice president of Toes Opto-Mechatronics, points out the optimization of the panel cutting tool allows it to cut thin glass efficiently. It also sends the cutting data to MES for yield calculation and cutter lifespan prediction. This is a typical application of Industry 4.0.

Imagination Technologies (IMG.L) announces that it was awarded a Partner of the Year Award from TSMC during the TSMC Open Innovation Platform (OIP) Ecosystem Forum. Imagination received this recognition in the Graphics IP category for its collaboration with TSMC to develop highly optimized reference design flows and silicon implementations using Imagination's industry-leading PowerVR Series6 GPUs combined with TSMC's advanced process technologies, including 16nm FinFET process technology.TSMC selects the winners for the partner award based on customers' feedback, the number of tape-outs and wafer shipment enabled by the IP, along with the strength of technical support offered by the company.Tony King-Smith, EVP marketing, Imagination, says: "We're delighted to receive this honor from TSMC. Our long-time collaboration is focused on helping our mutual customers get the most out of Imagination's IP combined with TSMC's advanced processes. This includes developing improved design flows and engineering guidance through PPA projects such as our PowerVR Series6XT GPU on 16nm FinFET."Suk Lee, TSMC senior director, Design Infrastructure Marketing Division, says: "This award recognizes Imagination's excellence in delivering leading-edge graphics technology on our advanced process nodes. Imagination's commitment to delivering the highest quality results and strong product differentiation, enables our mutual customers to speed their time to volume production in the most efficient way."Imagination and TSMC are also working together to optimize Imagination's IP platforms incorporating PowerVR multimedia IP, MIPS CPUs, Ensigma RPUs and OmniShield security technology with the broad portfolio of TSMC processes to dramatically reduce time to volume and R&D costs for creating next generation smart, connected SoCs for IoT, automotive, consumer, enterprise and mobile markets.About Imagination Technologies, please visit: http://www.imgtec.com/

Traditional network frameworks have been built over decades, which is hard to change overnight. Luckily, with SDN and NFV, the flexible and cost-saving framework simplifies deployment, setup, and maintenance, which help telcos build customer-centric business models."Dedicated hardware like routers, switches, and servers in telco facilities serve for fixed duties. Rigid frameworks make it hard to design and configure, let along catering to customer needs. However, SDN and NFV bring elasticity to the telecom industry," said Hadwin Liu, Chief Architect of NEXCOM Network and Communication Solutions Business Group.NFV incorporates multiple servers as a big virtual one in telecom facilities. Using resource management platform like OpenStack, telcos can view hardware resources and set rules based on service demands to provision computing, storage, or bandwidth resources automatically.NFV quickens application deployment like load balancing, QoS, and eMBMS. Under this framework, the next generation CPE with computing capability serves as a node in telco facilities, allowing telcos to reallocate nodes' resources and to offer security services like VPN, firewall, and UTM with less capital investments and less time to market.Programmable network frameworks facilitate operation and maintenance. SDN adopts software to define network forwarding rules. With pre-defined algorithms, software dynamically changes how network traffic is forwarded while automating the deployment, configuration, and management of networks.NEXCOM's communication platform supports open-source software for SDN and NFV implementation, helping telcos integrate server resources, coordinate network functionality, apply centralized control, and dynamically adjust network performance to enhance competitiveness with customer-centric services, applications and low TCO.For more information about NEXCOM, please visit http://www.nexcom.com/SDN and NFV provide a flexible, cost-saving framework, helping telcos build customer-centric business models.