Advanced Chip and Circuit Materials today announces the commercial availability of Celeritas HM50 and Celeritas HM001, which eliminate the root causes of warpage, package bow, solder fatigue, and high-frequency signal loss in large-format AI accelerators and advanced chip packaging architectures. Celeritas HM50 is a negative CTE (-8 PPM/°C) material and Celeritas HM001 is a near-zero CTE material. Used together in a single stackup, they bring board CTE below 10 ppm/°C while simultaneously delivering Tier 9 electrical performance.Every hyperscaler building AI infrastructure is confronting the same pair of converging constraints. As AI accelerators scale beyond reticle limits, thermomechanical mismatch between silicon (2–4 ppm/°C) and standard PCB materials (~18 ppm/°C) produces catastrophic reflow warpage, package bow, and solder joint fatigue. Simultaneously, the explosive growth in data rates, driven by HBM, UCIe, and chip-to-chip interconnect operating at 100+ Gbps, is pushing signal integrity requirements beyond what standard PCB dielectrics can support. The industry has been searching for two separate solutions to two separate problems. ACCM has built one material family that addresses both.The industry's leading proposed fix of solid glass substrates remains positive in CTE and does not address the electrical side at all. ACCM today announced Celeritas HM50 and Celeritas HM001, which together solve both problems simultaneously. Programs can start today.Celeritas HM50 FEA – Standard PCB at 18 ppm/°C (left) vs. PCB with HM50 at 10 ppm/°C (right). FR4 PCB baseline fails JEDEC qualification, while the PCB with HM50 shows >100× improvement. Warpage and Package Bow are reduced by 64%, and 81%, respectively. Combined HM50+HM001 stackups achieve even lower effective CTE.Keshav Amla, COO of Advanced Chip & Circuit Materials, said,"Rather than incrementally tuning stackups, we are applying a breakthrough materials innovation to remove a fundamental limitation that has constrained system scaling. HM50, with its negative CTE of -8 PPM/°C, drives the effective CTE of the board down. Even with heavy copper designs, you could tune a board down to 12, 10, 8 PPM/°C or lower. And where next-generation data rates demand extreme loss performance, HM001 replaces those layers with a Tier 9 loss material that has a near-zero CTE. Together, they give designers headroom they simply have not had before."The HM Class of materials matches each layer type in an AI accelerator stackup with a material purpose-built for it: HM50 for the power planes, HM001 for the signal layers. As AI accelerators grow in scale, the industry has long struggled with two separate problems — boards warping under thermal stress, and signal loss at extreme data rates. ACCM's Celeritas material family tackles both within a single solution. Celeritas HM50 counteracts the thermal expansion mismatch that causes warpage and solder joint failures, enabling designs that previously failed industry qualification to now meet it with significant margin. Celeritas HM001 addresses the signal integrity side, supporting the data rate demands of next-generation AI interconnects while also contributing to thermal stability. Together, the two materials give chip and board designers headroom that standard PCB materials have not been able to provide. For more details, please visit here.Credit: Advanced Chip and Circuit Materials

As artificial intelligence (AI) becomes increasingly sophisticated, the demand for higher processing power, speed and efficiency in computing has surged. Next-generation technologies, from enterprise data centers (EDCs) and AI PCs to the Internet of Things (IoT) and 6G communications, require unprecedented bandwidth. However, as data rates climb, ensuring signal integrity during semiconductor testing becomes exponentially more difficult. Even slight impedance mismatches or signal degradation can trigger false failures, compromise yields and delay critical product launches.To address these fundamental industry challenges, Smiths Interconnect, a Molex company, has introduced the DaVinci Gen V test socket. Built upon a patented mechanical foundation, this fifth-generation coaxial test socket provides an out-of-the-box solution engineered to overcome impedance tuning and signal degradation hurdles. The product rigorously tests semiconductor chips during manufacturing to ensure they deliver ultra-reliable, lab-grade accuracy in high-volume production environments.Core Mechanical InnovationsThe performance of the DaVinci Gen V is rooted in its core mechanical innovations. A new signal cavity design allows for superior impedance control, establishing a cleaner and more reliable signal path. This is achieved through enhanced conductor-to-ground concentricity, which minimizes signal degradation and surpasses all previous DaVinci series models. The socket utilizes spring probe technology featuring a homogeneous alloy plated with gold to ensure better grounding. These precision probes deliver a consistent, stable contact resistance averaging as low as 33 milliohms and boast a long contact life that has been tested up to 500,000 insertions.Electrical Performance and Signal IntegrityThe electrical performance of the DaVinci Gen V sets a new benchmark for semiconductor validation. Designed to overcome the physical challenge of scaling impedance for next-generation chips, the socket supports staggering digital speeds. It enables unprecedented signaling speeds of up to 224Gbps PAM-4 for AI accelerators and speeds beyond 100 GHz for future 6G networks.In terms of RF characteristics, the DaVinci Gen V delivers a bandwidth greater than 84 GHz at a -1 dB insertion loss. The architecture utilizes a short signal path with a 4.90mm test height and the impedance can be precisely tuned to match the system or be defined as needed.Operational and Manufacturing AdvantagesBeyond raw speed, the DaVinci Gen V is engineered for streamlined, scalable manufacturing. The socket accommodates high co-planarity and features a tri-temp design capable of operating in extreme environments ranging from -55°C to 150°C. This robust mechanical performance ensures that the exact same socket can be utilized across manual test, bench test and high-volume manufacturing production test stages, guaranteeing consistency.Recognizing that modern integrated circuits are rapidly growing in complexity and size, the DaVinci Gen V was designed to easily accommodate an increase in next-generation ASIC (application specific integrated circuit) sizes. Despite this scalability, it maintains full compatibility with existing test hardware and PCB socket footprints. This backward compatibility allows manufacturers to transition effortlessly, saving costs, reducing development cycles and significantly accelerating time-to-market. The socket is also highly serviceable in the field, permitting the replacement of a single probe or the full array, and can be cleaned while the system is running using a cleaning surrogate.Target End Markets and Proven ApplicationsThe broad capabilities of the DaVinci Gen V make it well suited for a wide range of advanced semiconductor applications. Target end markets include data center processors such as CPUs and GPUs, AI accelerators and ASICs, high-performance computing and tensor processors, network switches and FPGA-based 224G SerDes devices, as well as autonomous vehicle and ADAS chips. As demand for higher bandwidth and faster data processing continues to grow, these applications require increasingly stringent testing accuracy and signal integrity performance.Its effectiveness in high-stakes, high-volume environments is already proven. Since the product's launch, Smiths Interconnect has secured a key program with a leading technology company to support their advanced AI GPU accelerator chips.Building on this initial success, the company was subsequently awarded a next-generation accelerator chip program with the same partner. This continued partnership  underscores the superior performance, innovation, and reliability of Smiths Interconnect’s test socket technology.The DaVinci Gen V test socket redefines high-speed semiconductor testing by combining advanced, patented insulated metal technology with precision impedance tuning. It effectively eliminates measurement errors while guaranteeing lab-grade accuracy and repeatability in robust production settings. By enabling the reliable validation of high-bandwidth devices, the DaVinci Gen V ensures that manufacturers are fully equipped to meet the performance demands and future-readiness requirements of tomorrow's most complex integrated circuits. Contact Smiths Interconnect  to learn more.DaVinci Gen V supports AI accelerators, GPUs and data center processors. Credit: Smiths Interconnect

The global semiconductor industry is undergoing profound transformation-not only in process technologies and transistor density, but also in the composition of its workforce. Taiwan, the undisputed center of advanced semiconductor manufacturing, is increasingly attracting a new generation of technical talent: female engineers. By choosing Taiwan as the starting point of their professional journeys, these women are bridging the gap between academic training and industrial practice, while bringing fresh perspectives to a field that depends on precision, resilience, and collaboration.The Industrial Development Administration under the Ministry of Economic Affairs is committed to building a comprehensive support and training ecosystem for international talents in Taiwan. The program covers key semiconductor technologies, cross-cultural communication, and local integration, while also leveraging online learning resources that connect talent across regions.Designed to help outstanding international students and professionals transition smoothly into Taiwan's semiconductor industry, the initiative provides early exposure to the local industrial ecosystem and offers diverse mentorship and support services to strengthen long-term adaptation and career development in Taiwan. Through these efforts, Taiwan aims to foster a more inclusive environment for global talent while enhancing the international competitiveness of its semiconductor industry.Through the stories of Phan Thi Kim Ngan from Vietnam and Alyana Denise Ramirez from the Philippines, a broader narrative emerges-one defined by perseverance, cross-cultural adaptation, and a shared ambition to shape the future of technology.A Strategic Choice: Why Taiwan?For many aspiring engineers across Southeast Asia, Taiwan represents the pinnacle of the global semiconductor industry-a place where innovation is not only developed, but realized at scale.Alyana Denise Ramirez, an A3 EE Assistant Engineer at ASE and a student at I-Shou University, says she came to Taiwan driven by both purpose and opportunity. For her, working in Taiwan provides a critical pathway to career growth, allowing her to directly apply academic knowledge in real industrial settings.Phan Thi Kim Ngan, who recently completed her Master of Science in Electrical Engineering at National Yang Ming Chiao Tung University (NYCU), shares a similar perspective. Coming from Vietnam-a rapidly developing economy with strong momentum in manufacturing and services-she found Taiwan' highly specialized ecosystem in semiconductors, AI, and computer science to be a decisive attraction.  "Taiwan is the leader in semiconductor manufacturing in the world, and there is no better place to learn the most advanced technology in semiconductor than here," said Ngan.This close proximity to the "real industry" is one of the strongest motivations for international students who want to see their ideas move beyond the classroom and into production lines that power the global technology supply chain.The Female Edge in EngineeringWhen asked what unique perspectives female engineers bring to the industry, both women point to structured thinking, adaptability, and diversity in problem-solving.Alyana observes that female engineers often bring stronger attention to detail and greater creativity when addressing technical challenges. This helps prevent solutions from becoming one-dimensional and ensures that multiple perspectives are considered before final decisions are made.For Kim Ngan, building influence within a team - especially in multinational environments - is less about speaking the most and more about building reliability over time.By consistently following through on commitments and communicating clearly, she found that trust and influence develop naturally.The Philosophy of Consistent Small ImprovementsEntering the high-pressure world of semiconductor manufacturing and AI development can be intimidating. Kim Ngan recalls her early experiences in team discussions, where she often felt uncertain and hesitant to speak up.Rather than trying to solve every challenge at once, she adopted a philosophy of steady, incremental growth."Growth does not come from sudden breakthroughs, but from consistent small improvements," Kim Ngan says.This methodical mindset often meant spending nearly an hour preparing a single question for her supervisor-ensuring both clarity and confidence before speaking. Such discipline reflects the essence of engineering: breaking down complex challenges into manageable, solvable steps.Bridging Cultural and Communication GapsWhile technical challenges are significant, cultural adaptation can be equally demanding. For Alyana, the greatest challenge was not engineering itself, but language. "Chinese is not my forte," she admits, noting that learning Mandarin has been one of the most difficult aspects of both studying and working in Taiwan. She hopes to pursue a master's degree abroad in the future after gaining more professional experience and further advancing her career.Language barriers remain one of the key challenges in retaining international talent. Recognizing this, ASE provides Mandarin classes to support foreign employees' workplace integration. Alyana believes language is essential-not only for work efficiency, but also for building friendships and stronger professional relationships.Kim Ngan also observed distinct workplace differences in Taiwan, particularly in how professionals think, communicate, and present ideas during meetings. During her internship at Micron, she learned that even seemingly small pieces of data can influence decisions across multiple teams.This experience taught her that engineering is not only about technical accuracy, but also about how ideas are communicated, applied, and shared across highly collaborative environments.Corporate Support and the Pursuit of StabilityTaiwan's semiconductor companies increasingly understand that attracting talent is only half the challenge-retention is the true long-term priority. As a result, many companies are building workplace environments that emphasize employee well-being, career development, and long-term stability.Specialized Healthcare: ASE provides female-focused healthcare services, including pap smears and pregnancy-related health checkups through its on-site clinics.Mentorship: Supervisors and team leaders offer constructive feedback and help international engineers prepare for major presentations, reducing anxiety and strengthening confidence.Financial & Career Growth: Competitive salaries and clearly defined career development paths are key reasons many foreign professionals choose to remain in Taiwan long-term.Daily Life Stability: Public safety, convenient transportation such as HSR and MRT systems, and accessible 24-hour public amenities create a stable and low-stress living environment.Integration Beyond the WorkplaceLife for these engineers extends far beyond laboratories and cleanrooms. Integration into local communities often happens through shared everyday experiences-playing tennis with Taiwanese colleagues, gathering during Lunar New Year celebrations, singing together, and sharing traditional foods from home.Kim Ngan finds comfort in the similarities between Taiwanese and Vietnamese cuisine, while also enjoying introducing her colleagues to Vietnamese spring rolls. These moments of cultural exchange help foster the trust and mutual understanding that she believes form the foundation of strong teams.A Message to the Next GenerationBoth women share a clear message for young female students in their home countries: the opportunity is real, and the door is open.Alyana encourages them not to fear continuous learning or change. Kim Ngan offers equally practical advice: "You do not need to be fully ready to begin-you only need to be willing to make mistakes and keep learning."Taiwan's semiconductor industry is more than a collection of factories; it is an ecosystem that offers a genuine stepping stone for ambition, growth, and long-term career development.As Kim Ngan prepares to begin her full-time career at Micron following graduation, her journey stands as proof that with curiosity, persistence, and the right support system, the future of engineering is becoming increasingly global-and increasingly female.By emphasizing consistency, reliability, and the connection between theory and practice, these women are not simply participating in the industry-they are helping lead its transformation toward a more inclusive and innovative future.   

The global semiconductor landscape is undergoing a fundamental shift, moving from a focus on raw training power to the practical complexities of large-scale deployment. In an in-depth interview, Wallace Kou, President and CEO of Silicon Motion, detailed how the generative AI has evolved beyond its initial stages. While the market's early gaze was fixed almost exclusively on NVIDIA's GPUs, the High Bandwidth Memory (HBM), and the CoWoS advanced packaging technology, Kou argues that the industry is now entering the "Inference" era that is turning previous under-estimation about storage's importance on their head.The Shift from Training to InferenceThe turning point for this realization occurred during the NVIDIA GTC conference in March 2026. CEO Jensen Huang unveiled the Vera Rubin architecture, a move that signaled a massive spike in demand for NAND flash memory. During the initial AI boom, the industry was preoccupied with training massive models, a process that relies heavily on the lightning-fast throughput of HBM. However, as these models move into the inference phase - where they are actually used by end-users to generate content or solve problems - the access to context, historical data, and massive datasets storage become the primary bottleneck.Kou notes a dramatic shift in market sentiment. Only two years ago, storage was often an afterthought in the AI conversation; today, it is a critical scarcity. "There is currently not a single global cloud service provider or major smartphone manufacturer whose demand for DRAM and NAND is being fully satisfied," Kou observed. This supply-demand gap has triggered a financial windfall for storage module manufacturers and memory giants, with some stock prices skyrocketing up to tenfold as the market reacts to persistent shortages and rising prices.Technical Paradigm Shift: CMX and the Infrastructure of ThoughtAt the heart of this transition is a new architecture introduced by NVIDIA: the CMX Context Memory Storage platform. This architecture is designed specifically to handle the "KV Cache" (Key-Value Cache), which allows AI models to remember the context of a conversation or a complex task during the inference process.The hardware requirements for the CMX architecture are staggering in their scale and technical demands. Each individual Rubin GPU requires 16TB of dedicated storage to function effectively within this framework. At a system-level scale, a single NV72 Vera-Rubin setup can demand more than 1 Petabyte, or 1,000 Terabytes, of total storage capacity. Beyond mere capacity, the CMX architecture facilitates direct GPU access to storage, a feature that bypasses traditional latency bottlenecks and ensures that AI inference remains fluid and responsive.While this creates a massive commercial opportunity for the storage industry, it also places an unprecedented strain on NAND production. Kou emphasizes that this is not just a cloud-based phenomenon. The explosion of Edge AI - AI processed locally on devices - is further complicating the supply chain. For instance, driven by major players like Meta, the market for smart glasses is expected to reach 60 million units this year. These wearable devices require high-performance embedded storage, creating a secondary front in the war for NAND capacity.Silicon Motion's Role: Solving the QoS BottleneckAs the world's leading NAND controller maker, Silicon Motion sits at the intersection of these competing demands. The primary technical challenge in modern AI environments is maintaining Quality of Service (QoS). In a multi-tenant cloud environment, where multiple GPUs are accessing shared storage simultaneously for different inference tasks, data transfer speeds can often fluctuate or drop.To solve this, Silicon Motion has deployed its proprietary PerformaShape technology. This technology ensures that even under heavy, concurrent workloads, the transmission speed remains stable. By stabilizing these data flows, Silicon Motion has positioned itself as an "indispensable stabilizer" in the AI ecosystem.Beyond data path optimization, Silicon Motion is also extending its role into system-level infrastructure by providing enterprise-grade boot drives for leading AI GPU, TPU, and DPU platforms, ensuring system reliability and fast initialization at scale.The Crisis of Imbalance: Kou's "Capacity Persuasion" EffortsDespite the record-breaking revenues, Kou is deeply concerned about the "shadows" lurking behind this prosperity. The current memory market is suffering from a dangerous imbalance. To maximize profits and satisfy the insatiable hunger of AI cloud giants, major manufacturers like Samsung, SK Hynix, and Micron are funneling the majority of their capital expenditure (CAPEX) into HBM and DDR5 production.This strategic pivot has effectively "squeezed" the production capacity available for standard NAND flash. Kou warns that this "AI squeezing effect" could lead to a collapse in traditional sectors. Over the past eight months, Kou has embarked on a global mission, meeting with leaders at Samsung, SK Hynix, Kioxia, SanDisk, YMTC, and Micron. His message is one of "capacity persuasion": he is urging these giants to reserve a portion of their production lines for the automotive, PC, and smartphone industries."If these foundational industries break because they cannot find parts, Edge AI will have no 'soil' to grow in," Kou warned. He believes that a total focus on the high-margin AI server market could eventually backfire, destroying the broader technology ecosystem that supports AI development.A Stabilizing Strategy: From Cloud to EdgeSilicon Motion is positioning itself as the "transition enabler" for an industry in flux amid an expected 2–3 year supply shortage. As NAND manufacturers concentrate their internal resources on AI-driven initiatives, they are increasingly outsourcing non-core and mainstream projects, such as PCIe Gen5 controllers and embedded solutions. In this shift, Silicon Motion has emerged as a preferred partner to fill the resulting gap.At the same time, as rising prices weigh on demand in the PC and smartphone markets, the company is helping customers pivot toward automotive and AIoT applications, including rapidly growing segments such as smart glasses, which are seeing a surge in shipments this year.One of the most critical areas is the automotive sector, where Silicon Motion has spent a decade building a presence. While memory giants might see automotive requirements as "niche" or low volume compared to AI servers, Kou views them as essential to global stability. When major OEMs consider abandoning these specialized demands due to capacity constraints, Silicon Motion steps in to ensure the global automotive supply chain does not grind to a halt."We are not just looking for a surge in revenue; we want to fulfill our responsibility to the industry," Kou said. By providing stable controllers and storage solutions for AIoT and automotive applications, Silicon Motion is effectively repairing the cracks in a fractured global supply chain.Future Outlook: 2027 and BeyondThe current supply-demand imbalance is not a temporary glitch but a structural reality that Kou expects to persist until at least late 2027 or 2028. Several factors make it nearly impossible to add capacity quickly, for example, land acquisition is increasingly difficult. The lead time for building specialized cleanrooms and procuring critical equipment now exceeds one year.Kou predicts that while the DRAM shortage might begin to ease by the end of 2027, the relief for NAND will likely come even later. In this high-pressure environment, Silicon Motion's role as a key stabilizing force becomes increasingly important.Particularly in emerging sectors such as smart IoT and automotive applications, Silicon Motion delivers reliable controller and storage solutions, filling the vacuum left by production shifts at major manufacturers or by projects lacking sufficient engineering support.By helping global clients navigate the complexities of geopolitics and capacity wars, Silicon Motion aims to ensure that the AI revolution leads to a steady, sustainable future rather than a chaotic collapse of the broader tech industry.AI inference boom fuels supply-demand imbalance until 2027-2028, says Wallace Kou. Credit: Silicon Motion

As AI data center rapidly scales toward the gigawatt (GW) level, energy management is evolving from a supporting function into a defining strategic pillar. Against this backdrop, Infineon Technologies is redefining power infrastructure of AI era through its comprehensive "From Grid to Core" strategy, integrating energy efficiency, power density, and system resilience from the electrical grid to the processor core.Scaling AI: Strategic Power Solutions MatterThe evolution of artificial intelligence (AI) has accelerated far beyond the trajectory once predicted by Moore's Law. As AI models continue to expand in parameter scale and real-time inference becomes increasingly critical, demand for computing power is rising at an unprecedented pace.Today, the power consumption of a single GPU is rapidly approaching the kilowatt level, and the power density of a server rack has increased significantly from less than 60kW in the past to exceeding 100kW, now moving toward a new threshold in the megawatt range.This is not just numerical growth; it represents a fundamental shift in power architecture. As AI computing clusters expand rapidly, traditional 48V busbars and AC power distribution architectures are quickly approaching their physical limits in terms of power loss, thermal management, and spatial constraints.Adam White, President of Infineon's Power & Sensor Systems Division, emphasized that future competition in AI infrastructure will no longer be limited to chip performance. Instead, it will be a cross-disciplinary integration battle encompassing power electronics, materials technology, and system architecture.From Grid to Core: Rethinking the power delivery architectureAt this critical turning point for the industry, Infineon's competitive advantage lies not in a single breakthrough product, but in its ability to orchestrate and optimize the entire power delivery chain at the system level."From Grid to Core" is more than a product strategy - it is a multi-phase architectural framework designed to reshape the future AI energy chain. Developed through early collaboration with global hyperscalers and ecosystem partners, the strategy enables Infineon to address evolving AI power demands across every phase of infrastructure, from utility grids to processor-level power management.Power grid: Enabling a sustainable, high-efficiency power with HVDCAt the front end of the data center, power infrastructure is transitioning from traditional mechanical systems to highly integrated solid-state solutions. Future AI facilities are expected to increasingly adopt decentralized DC microgrids, enabling greater efficiency, flexibility, and resilience in energy management.By leveraging silicon carbide (SiC) technology in solid-state transformers (SSTs), system weight can be dramatically reduced - from nearly 20 tons to approximately 500 kilograms—while simultaneously improving overall energy efficiency by more than 1%. Beyond optimizing space utilization and operational costs, this advancement signals a broader industry migration from electromechanical infrastructure toward semiconductor-driven power systems.As SSTs and related technologies become integrated into AI power infrastructure, a multi-billion-dollar semiconductor opportunity is emerging across next-generation energy systems.At the same time, the power grid is evolving beyond its traditional role as just an energy source. Through digitally controlled power systems with real-time monitoring and remote management capabilities, combined with solid-state circuit breakers (SSCBs) featuring microsecond-level response times, the grid is becoming an intelligent energy platform capable of continuous optimization and predictive management.Server rack: Reshaping power density and maximizing efficiencyAs data centers advance toward GW-scale deployments, power distribution architecture is undergoing a fundamental redesign. Infineon is driving the industry's transition from traditional 48V systems to ±400V and 800V high-voltage DC architectures. Through the design of three-phase power sidecars, Infineon is restructuring power supply and computing systems to establish a more efficient and flexible power distribution model.At the same time, the power architecture of AI data centers is following a clear evolutionary path: moving from integrated server rack designs to high-voltage DC and sidecar power supply configurations, and ultimately advancing to gigawatt-scale infrastructures that incorporate DC microgrids.Meanwhile, The high-frequency characteristics of gallium nitride (GaN) components enable intermediate bus converters (IBCs) to achieve over 98% conversion efficiency and exceptionally high power density in an extremely compact form factor, significantly reducing power transmission losses and freeing up more space for AI computing resources.Processor core: Power density and new architectures for next-gen AI computeAt the processor core—the final stage of power delivery—the challenge shifts toward managing extreme current density and ultra-fast transient response.To support next-generation GPUs requiring massive current delivery and rapid load transitions, Infineon has introduced a digital multiphase PWM controller alongside the industry's first TLVR four-phase power module. These technologies are engineered to provide highly stable, efficient, and responsive power delivery for AI processors operating under increasingly demanding workloads.In response to the next generation of GPUs demanding ultra-high current and rapid load changes, Infineon has introduced digital multiphase PWM controllers and the industry's first TLVR quad-phase module. By leveraging high-precision telemetry and digital control technologies, power systems have transformed from energy suppliers into intelligent platforms capable of real-time monitoring, prediction, and optimization.From AI data center to physical AIIf data centers form the foundation of AI computing power, the physical world will be where AI's true value is ultimately realized. As AI increasingly expands into humanoid robots, autonomous systems, and intelligent manufacturing equipment, demands for energy efficiency, real-time responsiveness, and system reliability will become even more critical.Infineon is extending its long-established expertise in power management beyond data centers into the emerging era of Physical AI. By integrating sensing technologies, actuate, security and connectivity solutions, and high-efficiency power modules, the company is enabling a comprehensive functional blocks that empower humanoid robots to perceive, think, act and connect, safely and secured in a real-world environment.Push the boundaries of power technology in AI era"We Power AI" is not just a slogan for Infineon—it is a concrete commitment to the future of the industry. From gigawatt-scale data centers to physical AI, Infineon continues to push the boundaries of power technology, ensuring that every watt of energy is transformed into the greatest possible value for AI.As the industry advances toward the next generation of computing, energy management will become the decisive key to truly unlocking the full potential of AI. In this wave of transformation, Infineon is joining forces with ecosystem partners to stand at the forefront of defining the future.Editor's Note: Adam White will deliver a keynote address at COMPUTEX 2026 on June 4 titled  "Infineon Powering AI from Grid to Core to Physical AI."  The session will explore emerging trends and strategic opportunities in power infrastructure of AI era.Credit: Infineon

Solid State Storage Technology Corporation (SSSTC), a subsidiary of Kioxia Corporation and a leading global SSD provider, is showcasing its enterprise SSDs designed for immersion cooling and engineered for AI-driven data centers, along with a comprehensive portfolio of industrial and enterprise SSD solutions.As generative AI and high-density computing evolve, thermal management is critical. To address this, SSSTC has optimized its SSDs for immersion cooling environments by enhancing corrosion resistance through specialized materials, component protection, and structural design. The lineup includes the SATA ER3, ER4, and ER5 series, as well as the PCIe U.2 PJ1 and EJ5 series.These SSDs are optimized for immersion cooling environments, where systems are submerged in non-conductive dielectric fluids. By leveraging the high heat capacity and convective properties of liquids, heat can be efficiently dissipated through fluid circulation and heat exchange. This approach reduces reliance on traditional air cooling while improving Power Usage Effectiveness (PUE) and overall system reliability.SSSTC is also highlighting a range of industrial and enterprise SSDs optimized for AI and edge applications. Industrial SSDs support Edge AI and harsh environment deployments, with operating temperatures ranging from -40-degrees Celsius to 85degrees Celsius, along with anti-vibration and shock-resistant designs for outdoor and industrial environments. The pSLC architecture enhances endurance for sustained write-intensive workloads, while a multi-tier PLP (Power Loss Protection) framework -  including hardware PLP, firmware PLP, and PLN -  provides flexible data protection.Enterprise eTLC SSDs are designed to deliver stable performance for AI workloads, offering endurance options of 1 and 3 DWPD over a five-year period for varying workload intensities. Under sustained workloads, they maintain more than 90% random IOPS consistency, minimizing performance fluctuations. Firmware optimized for high-density computing enables low latency operation, while capacitor-based PLP and immersion cooling support ensure reliable performance in demanding deployment environments.With more than 18 years of in-house firmware development expertise, SSSTC understands diverse storage requirements across industries and provides flexible customization options, including configurable over-provisioning, lifespan and capacity optimization, performance and power tuning, and application-specific firmware development. SSSTC remains committed to helping customers build stable, efficient, and sustainable AI storage infrastructures.Founded in 2008, SSSTC became a subsidiary of Kioxia Corporation in 2020 and delivers high-quality SSDs through in-house firmware and NAND expertise. For more information, visit the SSSTC website.Remark: PCIe is a registered trademark of PCI-SIG.Credit: SSSTC

JMicron Technology Corp., a global leader in high-speed Bridge IC solutions, today announced it will unveil its flagship innovations at COMPUTEX 2026. Building on years of proven expertise in high-speed interface technologies and strong market recognition, JMicron will present a portfolio centered on extreme performance, intelligent backup, and hyperscale expansion, demonstrating its continued momentum in advancing the digital storage ecosystem.In response to the stringent demands for performance and data protection in big data and professional storage markets, JMicron introduces three key controllers: JMS591, JMS591U, and JMB595.JMS591 is purpose-built for multi-bay HDD array applications, supporting USB 20G and eSATA interfaces. In RAID 0 mode, it delivers read/write performance exceeding 2000 MB/s, providing a powerful foundation for NAS and DAS systems.JMS591U targets enterprise and professional users, integrating JMicron's exclusive Offline Clone & Erase technology. It enables 1-to-4 high-speed duplication and DoD-compliant data sanitization, offering a one-touch solution for data migration and security compliance.JMB595 is a high-performance PCIe Gen4 x4 to 16-port SATA III expansion controller. Through cascading architecture, it can scale to connect up to 240 storage devices, ideally suited for hyperscale data centers and surveillance storage infrastructures."JMicron has long been committed to transforming complex high-speed transmission technologies into intuitive and powerful hardware solutions," said Ming-Cheng Lin, VP of Sales and Marketing at JMicron."The products showcased at COMPUTEX not only push storage performance beyond the 2000 MB/s milestone, but also precisely address customers' critical needs in large-capacity storage and security compliance through integrated RAID engines and offline cloning technologies. We are not merely a chip supplier—we are a strategic partner helping customers build a solid foundation in the data-driven era."JMicron cordially invites global partners and media representatives to visit its booth at COMPUTEX 2026. Through face-to-face engagement and forward-looking technology demonstrations, JMicron looks forward to exploring the future of storage innovation together and ushering in a new era of high-efficiency data transmission and intelligent data management.

VIA Labs, Inc. (VLI), a leading supplier of USB4, DisplayPort, SuperSpeed USB, and USB Power Delivery Controllers, today announced the launch of its first MST Hub VL610 at Computex 2026. Following the market success of the VL605 USB-C to HDMI 2.1 signal converter, VL610 is a new-generation chipset designed to address the growing demand for multi-display expansion. Supporting up to three high-resolution displays simultaneously, it sets a new benchmark for USB-C docking solutions. Attendees can learn more about VLI's products during Computex 2026 at Booth N0614 in Hall 1, Taipei Nangang Exhibition Center.The VIA Labs VL610 is a highly integrated DP 2.1 HBR3 Multi-Stream Transport (MST) hub designed for USB-C docking stations and high-end video adapter applications. Compared to its predecessor VL605, which supports a single HDMI 2.1 output, VL610 significantly enhances display performance. VL610 series includes two SKUs: VL610 supports three video outputs, while VL610D supports two video outputs, addressing different docking design needs. Its flexible architecture includes one fixed HDMI 2.1 FRL transmitter, one configurable port supporting DP++ or HDMI 2.1 FRL, and a third configurable port supporting DP++ or HDMI TMDS (VL610 only). VL610 supports a single display up to 8K60Hz or 4K240Hz, and up to three displays at 4K60Hz or QHD144Hz. It also enables up to six independent audio and video streams, with a single DP output supporting up to four MST streams. Full support for color formats and audio ensures a high-quality multimedia experience.In terms of advanced display technologies, VL610 integrates a DSC 1.2a decoder, supporting decompression to HDMI output or direct pass-through to compatible displays. It also supports cross-platform Variable Refresh Rate (VRR), delivering smooth visuals for high-end gaming and professional imaging applications. VL610 also integrates ECDSA-256 asymmetric authentication, enabling secure firmware updates and protection against malicious firmware attacks.VL610 also features a unique Logo Bitmap display capability with event-triggered graphics. It can display brand logos, warning messages, or guidance screens in scenarios such as host disconnection, USB-C port anomalies, or link errors, helping users quickly identify and resolve issues. This feature enables brands to proactively communicate with users during idle or fault conditions, enhancing both brand visibility and user experience."VL610 represents a key milestone in VLI's multi-display signal conversion technology. Evolving from the single HDMI 2.1 output of VL605 to the triple-stream architecture of VL610, we have translated customer needs into product innovation. VL610 is positioned to become the core chipset for next-generation high-end USB-C docking stations, further strengthening VLI's leadership in USB-C display interface solutions.", said Wayne Chang, Director of PM at VIA Labs.

AGI Technology will showcase a diverse lineup of next-generation storage products at COMPUTEX 2026, centered around this year's core theme: "Think Big, Build Grand." Highlighted exhibits include DDR5 R-DIMM, PCIe Gen5 SSDs, and new additions to the AGI Smart Life industrial solution series. Additionally, AGI will feature its patented thermochromic heat-dissipation memory, alongside a strategic collaboration with StorArt on memory cards and a major external storage lineup featuring a heavyweight Japanese anime crossover.AGI is aggressively expanding into the extreme gaming and edge computing markets, empowering users to build a more robust foundation for high-performance computing.AI Solutions: Debuting DDR5 R-DIMM Server Memory to Launch a New Era of AI ComputingAs AI server performance bottlenecks shift toward memory bandwidth, AGI provides robust data throughput for next-generation processor platforms to meet the demands of AI computing and big data analysis. The initial rollout features mainstream high-speed specifications of 5600 MT/s and 6400 MT/s, with capacity options of 32GB and 64GB. Utilizing strictly screened high-quality original ICs, these modules ensure extreme stability and signal integrity under continuous 24-hour high-load environments—a storage solution tailor-made for next-generation AI data centers.Crossover Innovation & Major Collaboration | Expanding Industry Horizons and Unleashing the Hardcore Spirit of DAN DA DANAGI is expanding industry horizons through a strategic partnership with StorArt, pushing performance to new heights. A major highlight is the heavyweight crossover with the hit anime DAN DA DAN, featuring high-end internal DRAM, SSDs, and a brand-new Rugged External SSD (ED268). This powerhouse combines USB 20Gbps speeds with IP-rated durability and 2-meter drop protection. By merging elite tech with pop culture, AGI invites the world to embrace a "Bold" attitude at COMPUTEX 2026！Smart Life Solutions | Entering the Industrial Market with Grade-A Applications to Build a Reliable Foundation for Edge ComputingTo meet the rising demand for high-frequency data processing and edge computing, AGI's "Smart Life" series delivers industrial-grade solutions engineered for harsh environments. This specialized storage lineup ensures absolute data and video integrity with "Zero-Frame-Loss" performance.During the exhibition, the AGI booth will feature five major themed experience zones. Visitors who complete the stamp collection challenge can redeem an exclusive specialty coffee and enter a lucky draw for a chance to win premium DRAM products valued at over NTD10,000.AGI sincerely invites all content creators, gaming enthusiasts, and storage technology professionals to visit our booth and explore the new possibilities of next-generation storage.Join AGI at COMPUTEX 2026 from June 2–5 at Taipei Nangang Exhibition Center, Hall 1, 4F. Visit us at Booth L1117a to explore our latest innovations.AGI introduces new memory solutions engineered for peak performance.Credit: AGI

ZEISS, a global leader in optics and optoelectronics, will bring the quality discussion to the official COMPUTEX 2026 Forum stage for the first time this year, highlighting the growing role of quality in scaling AI hardware.As demand for AI infrastructure accelerates, quality is shifting from a manufacturing support function to a direct driver of performance, yield and delivery readiness. While public attention often centers on AI models, ZEISS says reliable hardware execution is becoming a decisive factor in AI deployment.Behind every AI interaction are massive data centers powered by thousands of GPUs. As systems scale from chip to rack, defects in semiconductor packaging, printed circuit boards (PCB/A), cooling systems and high-speed interconnects can affect uptime, deployment speed and total cost."With compute demand surging, manufacturers face record orders, but the challenge is delivering at scale with consistent quality," said Clive Yen, Global Head of Electronics Customer Segment, ZEISS Industrial Quality Solutions. "As systems grow more complex, quality becomes critical to reliable deployment. This is why we work across Taiwan's ODM ecosystem and the full AI server value chain to enable consistent, scalable quality.""At scale, even small defects can become major bottlenecks," said Tonmoy Kundu, Global Head of Sales, ZEISS Research Microscopy Solutions. "Manufacturers need faster insight, tighter process control and trusted failure analysis to accelerate next-generation AI hardware."ZEISS says it offers one of the industry's most comprehensive quality portfolios across the AI hardware value chain, supporting customers from semiconductor packaging and PCB inspection to liquid cooling, optical connectivity and final rack integration.At the forum, ZEISS will showcase solutions for advanced high-bandwidth memory (HBM), where rising stack heights and shrinking interconnect dimensions require high-resolution, non-destructive inspection and deep defect analysis.The company will also present metrology solutions for co-packaged optics (CPO), where ultra-tight tolerances for FAU and MPO connectors are essential to maintain alignment, coupling efficiency and long-term transmission reliability in 51.2T+ networks.At the exhibition hall (Booth J1109 | TaiNEX Hall 1, Taipei), ZEISS will showcase technologies spanning wafer process control, advanced packaging, X-ray inspection, electron microscopy, light and digital microscopy, and coordinate measuring machines. Applications will focus on chip manufacturing, PCB reliability, thermal management systems, connector quality and L10-L11 rack mechanical parts assembly.COMPUTEX 2026 runs June 2-5 in Taipei, where ZEISS will position quality as a foundational enabler of the next wave of AI growth. ZEISS will speak at the official COMPUTEX 2026 Forum on June 4, 4:30 p.m. to 4:55 p.m. at TaiNEX 2, Room 701, presenting "Quality Innovation Across the AI Chip-to-Rack Stack." The session will feature Tonmoy Kundu and Clive Yen.