Huawei has formally introduced its "Tau Law," proposing a shift from traditional process-node scaling to "time scaling," a model aimed at improving chip performance through optimisation across components, circuits, chips, and systems, even under mature process technologies.
Peking University researchers have unveiled a prototype electronic design automation (EDA) tool built for "true-3D" chip design, offering a potential missing link for Huawei's LogicFolding architecture and its broader Tau (τ) Scaling Law roadmap.


