With the 2025 OCP APAC Summit set to kick off next week in Taipei, industry attention is turning toward the next wave of AI and high-performance computing (HPC) infrastructure.
As generative AI pushes data center infrastructure to new limits, pressure is mounting on thermal management, interconnect design, and ecosystem interoperability. Ahead of the 2025...
As AI workloads hit data movement bottlenecks, MIT spinoff Lightmatter is betting that photonics, not more transistors, holds the key to next-generation infrastructure. After years...
Broadcom has launched its latest Tomahawk Ultra Ethernet switch chip, fabricated using TSMC's 5nm process, targeting high-performance AI infrastructure with a design aimed squarely...
Nvidia's selective opening of its NVLink interconnect technologies to partners is drawing scrutiny from across the semiconductor supply chain. While pitched as a collaborative gesture,...
At this year's COMPUTEX keynote, Nvidia CEO Jensen Huang unveiled NVLink Fusion, a new initiative to open the company's proprietary NVLink interconnect to third-party ASICs and CPUs...
The Ultra Accelerator Link (UALink) Consortium has officially become a legal entity, establishing itself to set a new high-speed, low-latency communication standard for AI data center...
Astera Labs, a manufacturer of high-speed transmission interface chips, has announced the debut of a new switch chip series and the official joining of the UALink alliance. The company...
The Ultra Accelerator Link (UALink) alliance, which saw the gathering of many IT giants, is committed to challenging the NVLink ecosystem, an AI chip accelerator interconnect technology...
