Following its North America technology forum, TSMC held the Hsinchu session on May 14, 2026. The company said the smart revolution is beginning, with AI evolving from generative AI and agentic AI to physical AI, driven by the power efficiency and performance of advanced semiconductor technology.
TSMC said the semiconductor market, once forecast to hit the US$1 trillion milestone in 2030, is now expected to surpass US$1 trillion in 2026 and reach US$1.5 trillion in 2030. Most of that growth will come from HPC and AI, which account for 55% of the market, while smartphones make up about 20%, and automotive and IoT each account for around 10%.
The company added that as AI shifts from training to broader deployment, inference is becoming increasingly important. Large language models generated by AI process text tokens, such as words or pixels in images, to improve productivity and create more value, which in turn is driving further investment in AI systems and sustaining demand for silicon products that power AI.
A13 set for 2029 production
In advanced logic, TSMC said A13 is a direct shrink of the A14 process and offers fully backward-compatible design rules, allowing customers to port designs quickly. A14 remains on track for mass production in 2028, A13 is expected in 2029, and A12 with Super Power Rail is also planned for mass production in 2029.
A14 is TSMC's second-generation nanosheet transistor process and uses NanoFlex Pro to improve power, performance, and area (PPA). Compared with N2, A14 delivers up to 15% faster speed at the same power, up to 30% lower power at the same speed, logic density at about 1.23x N2, and chip density at about 1.2x N2.
2nm family moves ahead
On the 2nm front, N2 began mass production in the fourth quarter of 2025. N2P remains on track for mass production in the second half of 2026, while A16 with Super Power Rail is expected to be production-ready in the second half of 2026.
TSMC also highlighted UHP3MIM, which offers capacitance density above 500fF/μm2 and is designed to improve power integrity for AI/HPC products. N2X and N2U, both aimed at further PPA gains, are scheduled for mass production in 2027 and 2028, respectively.
N2U is an extension of N2P and uses design-technology co-optimization to offer a balanced option for AI, HPC, and smartphone applications. Compared with N2P, N2U provides 3-4% faster speed, 8-10% lower power, and up to 3% higher logic density.
TSMC said transistor architecture has evolved from planar structures to FinFET and then to nanosheet. Beyond nanosheet, vertically stacked nFET and pFET, known as complementary field-effect transistors (CFET), are a possible scaling candidate.
The company recently demonstrated the world's smallest working 6T SRAM memory cell, with a footprint about 30% smaller than a conventional nanosheet design while maintaining similar design rules. It also showcased CFET ring oscillators built with about 1,000 transistors.
CoWoS yields exceed 98%
In 3DFabric, TSMC said it has already produced the world's largest 5.5x reticle-size CoWoS in 2026, with yields above 98%.
Over the next five years, CoWoS will continue to scale in size each year to integrate more logic and HBM dies. A 14x reticle-size CoWoS that integrates 20 HBM stacks is slated for mass production in 2028, while a version that integrates 24 HBM stacks and exceeds 14x reticle size is expected to be ready in 2029.
For system-on-wafer technology, TSMC-SoW can integrate logic and HBM dies to address the growing compute requirements of AI training.
SoW expands the interposer size to more than 40x reticle size, allowing integration of up to 64 HBM stacks and 16 compute chips. SoW-P for logic-die integration has been in mass production since 2024, while the more advanced SoW-X technology, which integrates logic and HBM dies, is expected to be ready in 2029.
Compared with 2.5D interconnect CoWoS, 3D interconnect SoIC offers 56x the connection density and 5x the power efficiency. N7-to-N7 SoIC with a 9μm bond pitch has been in mass production since 2023, and the 6μm bond-pitch version entered production in 2025.
SoIC technology will continue shrinking to N2-to-N2 stacking with a 6μm bond pitch, expected to begin mass production in 2028, followed by A14-to-A14 stacking with a 4.5μm bond pitch in 2029.
First 200Gbps MRM with COUPE due in 2026
In compact universal photonic engine (COUPE) technology, TSMC said the integrated co-packaged optics (CPO) solution can deliver 4x better power efficiency and 90% lower latency when COUPE on substrate is used, compared with traditional copper wiring. Using COUPE on the interposer can further improve performance, achieving 10x better power efficiency and 95% lower latency.
The world's first 200Gbps micro-ring modulator (MRM) with COUPE technology is set for mass production in 2026, with a bit error rate below 1E-08. TSMC is also expanding to 400Gbps modulators, multi-wavelength technology, and multi-row fiber-array units, targeting 4Tbps/mm bandwidth density by 2030.
Specialty process progress continues
TSMC said N3A is currently the most advanced logic process in the automotive segment and expects more than 10 new tape-outs. Automotive qualification for N3A was completed in the fourth quarter of 2025. N2P's Auto-Use process design kit (PDK) can support design work for autonomous vehicles and emerging physical AI applications. N2A, based on N2P, is the first nanosheet technology for automotive use and is expected to receive qualification in the first quarter of 2028.
In advanced RF technology, N4CRF is currently the most advanced RF CMOS process. Compared with N6 RF+, it can deliver 39% lower power and 33% smaller area for digital-intensive RF SoC products such as smartphones and AI-powered glasses.
Newly developed features include 0.5V standard cell components, high-gain FET development that can lift maximum oscillation frequency (fmax) by up to 15%, and low-noise FETs that can reduce noise by 30%.
In non-volatile memory, TSMC is advancing MRAM and RRAM as it continues shrinking from 40/28/22nm to 16/12nm.
RRAM at 40/28/22nm has been in mass production since 2022. 12nm RRAM is ready for customer tape-outs, 28/22nm RRAM has passed Automotive Grade-1 certification, and 12nm RRAM Auto is scheduled for launch by the end of 2026. 22nm MRAM has begun mass production, 16nm MRAM is ready for customer tape-outs, and 12nm MRAM, designed to improve logic density and performance, is under development and expected to be ready by the end of 2026.
In display technology, TSMC announced the industry's first FinFET high-voltage platform for foldable and thin OLED panels and AR glasses. Compared with N28HV, N16HV is expected to raise gate density by 41% and cut power by 35% for high-end smartphones. N16HV also offers a platform for backplanes used in near-eye display engines, reducing die area by 40% and power by 20% versus 28nm.
TSMC also said it is accelerating fab expansion. N2/A16 capacity is expected to ramp quickly, with a 70% CAGR from 2026 to 2028, while N3 and N5 capacity will expand at a 25% CAGR from 2022 to 2027. The company expects first-year wafer output for N2 to be 45% higher than N3.
Customer demand for AI accelerators is expected to grow 11x from 2022 to 2026, while demand for large die wafers is projected to increase 6x. TSMC said it will continue aggressively expanding CoWoS and SoIC capacity, with a CAGR of more than 80% from 2022 to 2027.
Article translated by Charlene Chen and edited by Jack Wu
