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AMD's investment in photonics and modular architecture signals shift in AI infrastructure development

Amanda Liang, Taipei
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Credit: AMD

AMD is positioning itself to address the future needs of artificial intelligence (AI) computing through advances in chip design and system architecture, particularly by integrating photonics technology and modular rack-scale platforms. CTO Mark Papermaster, speaking in a recent interview, highlighted how AMD's evolving engineering strategies will shape AI hardware capabilities and scalability over the next several years.

As AMD continues to shift from early Zen architectures to its latest Instinct GPUs and Helios rack designs, bandwidth remains a critical bottleneck within chip interconnections and memory interfaces. Papermaster explained that while photonics has been widely used for lateral scaling in large data center clusters, it has yet to be broadly adopted for vertical scaling in high-density clusters. One primary barrier is cost, with copper cabling currently providing a lower-cost, reliable solution, as evidenced by AMD's 72-GPU Helios node configurations. However, as cluster sizes expand to thousands of nodes and demand for higher density grows, the economics of photonics are expected to improve.

AMD anticipates an economic inflection point for photonics technology within the next three years as supply chains mature and manufacturing scales. Photonics is projected to gain traction in applications requiring high-density, large-scale AI hardware, while copper cabling will continue to serve diverse use cases due to its cost-effectiveness and reliability. This transition reflects a broader trend in the semiconductor industry toward integrating optical interconnects to overcome bandwidth and power limitations inherent to electrical connections.

AMD's evolving approach to AI hardware

Reflecting on AMD's trajectory, Papermaster noted that a decade ago it seemed unlikely the company would simultaneously lead in CPUs, GPUs, and AI infrastructure. Since then, AMD has undergone substantial transformation across core architecture, chip packaging, and foundry partnerships, and is now investing aggressively in rack-scale system design to support the growing AI workloads worldwide. Papermaster expressed confidence that the next-generation Instinct GPUs, paired with Helios rack platforms, will enable comprehensive AI training and inference at unprecedented scale, supporting not just thousands but hundreds of thousands of GPUs.

This evolution requires sustained investment in infrastructure alongside multi-generational product development and an engineering culture willing to embrace significant risk—principles championed by CEO Lisa Su and Papermaster himself. In 2025 alone, AMD acquired more than a dozen companies, enhancing capabilities in AI model development, photonics, and optical engineering. Its largest acquisition, ZT Systems, broadened AMD's expertise to include "true co-design" at the rack level, critical for creating integrated AI systems.

Partnerships with foundries such as TSMC and hyperscale data centers are pivotal to AMD's roadmap, enabling collaborative model development and the large-scale deployment of AI hardware. AMD also aims to expand its customer base through modular system designs that accommodate varying demand across enterprise, edge, and PC environments, moving beyond solutions tailored solely for data center workloads. Today, AMD supports AI models featuring up to 100 billion parameters on general-purpose AI PCs.

Papermaster emphasized that developing modular architectures is key both for vertical optimization within rack-scale systems and for horizontal competition and collaboration among teams. This modularity is regarded as a significant opportunity for growth and innovation in AMD's pursuit of AI computing leadership. The company's strategic focus on balancing traditional copper interconnects with emerging photonics technologies, coupled with deeper integration across hardware and software ecosystems, seeks to address the complex challenges of scaling AI infrastructures for the future.

Article translated by Jingyue Hsiao and edited by Joseph Chen