Synopsys has announced its continued, close collaboration with TSMC to deliver advanced EDA and IP solutions on TSMC's most advanced process and 3DFabric technologies to accelerate innovation for AI and multi-die designs.
The company stated that the two entities have collaborated for decades to advance the development of chip designs incorporating billions to trillions of transistors for AI applications. Industry leaders have embraced Synopsys AI-driven EDA flows, powered by Synopsys.ai, for their advanced chip designs on N2.
Furthermore, Synopsys is partnering with TSMC to enhance backside routing capabilities that enable TSMC's A16 process within the Synopsys digital design framework. This collaboration aims to improve power distribution and signal routing for optimal design performance and density. Interoperable process design kits (iPDK) and Synopsys IC Validator physical verification runsets are accessible for design teams to manage the escalating complexity of physical verification regulations and effectively migrate designs to TSMC N2 technology.
To enhance chip design efficiency, Synopsys and TSMC have facilitated the deployment of Synopsys EDA tools on the cloud via TSMC's Cloud Certification, offering joint clients cloud-compatible EDA tools that ensure precise quality of outputs and connect effortlessly with TSMC's advanced process technology.
Synopsys' cloud-certified tools include synthesis, place and route, static timing and power analysis, transistor-level static timing analysis, custom implementation, circuit simulation, EMIR analysis, and design rule checking.
"Synopsys' certified Custom Compiler and PrimeSim solutions provide the performance and productivity gains that enable our designers to meet the silicon demands of high-performance analog design on the TSMC N2 process," said Ching San Wu, corporate VP at MediaTek, in Synopsys' statement. "Expanding our collaboration with Synopsys makes it possible for us to leverage the full potential of their AI-driven flow to accelerate our design migration and optimization efforts, improving the process required for delivering our industry-leading SoCs to multiple verticals."
In addition, Synopsys, Ansys, and TSMC have collaborated to address the complex multi-physics challenge for multi-die designs with a comprehensive system analysis flow by leveraging their prime solutions. The most recent flow based on Synopsys 3DIC Compiler unified exploration-to-signoff platform, which integrates 3DSO.ai, combined with Ansys RedHawk-SC power integrity signoff platform for digital and 3D integrated circuits, enhances the thermal and IR-aware timing analysis.
Synopsys 3DIC Compiler is a TSMC-certified platform supporting 3Dblox, TSMC's 3DFabric, which includes TSMC-SoIC (System on Integrated Chips) and CoWoS packaging technologies.
Synopsys' complete multi-die test solutions, which include the Synopsys UCIe and HBM3 IP, ensure multi-die package health during factory testing and in the field, according to the company. Synopsys has collaborated with TSMC to tape out a test chip using TSMC's CoWoS interposer technology, which has full test, monitor, debug, and repair capabilities.
Synopsys reported that the company has achieved multiple silicon successes for UCIe and HBM3 IP solutions across N3E and N5 process technologies, accelerating IP integration and minimizing risk. The latest developments of the Synopsys UCIe IP, operating up to 40G, allow maximum bandwidth and energy efficiency without the need for additional area while the HBM4 and 3DIO IP solutions accelerate heterogeneous integration of 3D stacked-dies on TSMC's advanced processes.
"For decades, Synopsys has closely collaborated with TSMC, providing mission-critical EDA and IP solutions spanning all generations of TSMC's most advanced nodes," said Sanjay Bali, SVP of EDA product management at Synopsys. "This partnership has been instrumental in helping our mutual customers accelerate their innovation in the AI era and advance the future of semiconductor designs. Together, we are pushing the boundaries of what's possible, enabling groundbreaking advancements in performance, power efficiency, and engineering productivity."
"TSMC is excited to collaborate with Synopsys to develop pioneering EDA and IP solutions tailored for the rigorous compute demands of AI designs on TSMC advanced process and 3DFabric technologies," said Dan Kochpatcharin, head of the ecosystem and alliance management division at TSMC. "The results of our latest collaboration across Synopsys' AI-driven EDA suite and silicon-proven IP have helped our mutual customers significantly enhance their productivity and deliver remarkable performance, power, and area results for advanced AI chip designs."
Synopsys' collaboration with TSMC. Credit: Synopsys
