X-Fab Silicon Foundries, an analog/mixed-signal and specialty foundry, and crowd-sourcing IC platform partner Efabless, has announced the silicon availability of the Efabless RISC-V system on chip (SoC) reference design. This open-source semiconductor project went from design start to tape-out in less than three months using the Efabless design flow based on open-source tools, they said.

The mixed-signal SoC, called Raven, is based on the community developed ultra-low power PicoRV32 RISC-V core. Efabless has successfully bench-tested the Raven at 100MHz, and based on simulations the design should be able to operate at up to 150MHz, they added.

Raven utilizes X-Fab proprietary analog IP and is created with an open-source design flow. This hybrid open-source design brings the power of open innovation and at the same time protecting significant investment in proprietary IP, they said.

Efabless and X-Fab chose to manufacture the Raven on X-Fab's XH018 process, a 180nm 6-metal process with a wide variety of options including a low power option, on-chip isolation for high voltages, and high-temperature flash memory. X-Fab's XH018 process meets automotive quality requirements, they said.

The semiconductor design is fully functional and Efabless is now engaged with its initial customers on design of derivative offerings, they said.

"The successful partnership with Efabless demonstrates X-Fab's continued commitment to open-source semiconductor development," said Ulrich Bretthauer, product marketing manager at X-Fab. "Nearly 75% of Raven's die area is covered by X-Fab standard library blocks and macros. Using these proven IP blocks increased the reliability of the Raven while minimizing first-silicon risk."