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Global Unichip utilizes Cadence analog IP to implement WiGig-enabled SoC on 28nm process
Press release; Jessie Shen, DIGITIMES

Cadence Design Systems has announced that Global Unichip achieved first-silicon success integrating tri-band analog front-end (AFE) intellectual property (IP) with WiGig (IEEE 802.11ad), enabling integration of digital logic and analog monolithic die in an advanced 28nm complementary metal-oxide semiconductor (CMOS) process. The availability of the silicon-proven Cadence tri-band AFE IP running at 3.5 Giga-samples per second (GS/s) saved GUC's end customer over a year of total development time.

The tri-band AFE IP is available for immediate integration and tapeout, according to Cadence.

The WiGig specification enables near-field streaming of uncompressed HDTV content and has emerged as a leading innovation to cut the HDMI cord in TV entertainment rooms, as well as flexibly extend the HDTV experience into other venues, Cadence said. Citing ABI Research, Cadence indicated that over 1.5 billion chipsets with 802.11ad will be shipped in 2018.

The tri-band AFE IP includes WiGig (802.11ad) and Wi-Fi (802.11n or 802.11ac), and enables the throughput rate of up to 3.5GS/S needed to support uncompressed HDTV video. The AFE IP contains new dual-analog-to-digital converter (ADC), dual-digital-to-analog converter (DAC), phase-locked loop (PLL), oscillator and fast wake-up functions. The IP provides customers the flexibility to build SoCs for applications including Internet of Things (IoT), tablets, PCs, shared workstations, media hubs, network-attached storage (NAS), set-top boxes and digital/HDTVs.

"The wireless market continues to evolve quickly with demand for higher throughput requirements. We are investing in this emerging area to have the expertise to accelerate our customer's product time to market," said Yawlin Hwang, worldwide sales VP of Global Unichip. "We chose to work with Cadence on this emerging market segment as they not only offered the silicon-proven AFE IP, they also surpassed the performance requirements for the interface."

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