For much of the history of the semiconductor industry, Moore's Law was the industry's driver. Though Moore's law remains a strong and vibrant driver today, it has been joined by economic pressures, namely the cost requirements of continued technology progress.
These "Techonomic" pressures are increasingly exerting influence on semiconductor players, especially as they migrate to even smaller geometries. Digitimes recently has the opportunity to speak about such challenges with Aart de Geus, CEO of electronic design automation (EDA) provider Synopsys.
Q: Can you tell us in your own words how you would define techonomics, how it relates to Moore's Law at extreme geometries, and what are some of the challenges techonomics brings to players in the semiconductor industry?
A: Though it has never been easy to track Moore's Law, today's need to go beyond mere scaling, and to deal with atomic level physics, has taken the economic pressures to a new level.
Not everyone can play at the very leading edge of Moore's Law. The increasing cost of design limits the number of companies who can design at the very leading edge. The ever increasing costs of providing R&D and building leading-edge fabs also limits the number of semiconductor companies who can manufacture at the leading edge.
Techonomics has driven the extreme restructuring of the semiconductor industry that we are witnessing today. We have seen the rise of the Fab Lite model with long standing IDMs becoming dependent on foundries for leading-edge process development. We have seen semiconductor companies band together to share the burden of advanced process R&D. We are seeing semiconductor companies divest and acquire business lines to achieve the critical mass required to compete in today's environment.
Likewise, this puts pressure on the EDA tools that design companies choose. As fewer semiconductor companies have the ability to differentiate on process, differentiating on design becomes much more important. As evidenced by the recent phenomena of 'primary EDA vendor' pronouncements by such companies as Intel, National, Matsushita and Renesas, increasingly, semiconductor companies are turning to a single EDA company to provide a complete, comprehensive and correlated design flow.
Q: In terms of the Moore's Law shifting from a desire for more power (PC focused market) to integration and power-savings (a mobile and CE focused market), how has this changed the challenges for various industry players (designer, foundry, SATS, EDA, etc.), being that complexity is driving the industry? Can you comment on some of the issues Synopsys sees companies facing in terms of power and yield optimization on leading edge technologies dealing with such complexity? And how is Synopsys working to optimize power and yields for designers?
A: For years, designers designed to two key constraints: speed and area (which translates to cost). At nanometer geometries, power and yield have joined these two as primary considerations. Today, power and yield are equally if not more important than the traditional constraints of speed and area. To comprehend these constraints, the design tools need a strong understanding of the foundry process. This is achieved only through strong collaboration and through the ability to model the manufacturing process within the design tools.
Today we see leading semiconductor vendors choosing to collaborate very closely with a very small number of EDA vendors. Since the collaboration is more intense, they cannot afford to work with more than a select few vendors.
Likewise, the design tools must be constantly improved to comprehend the issues of power and yield, and this can only be done through strong collaboration with semiconductor companies. The major difference in the design flow today is that as the tools optimize one of the constraints, they also have a strong (often negative) impact on the other constraints. So, the tools may optimize power but in doing so decrease the speed of the chip. If the optimizations are done at different times in the flow or if the tools are not correlated, a ping-pong effect can be created, where the design iterates between design steps, optimizing a single constraint at the expense of others. For this reason, all the constraints must be considered together at the same time.
Q: What are the advantages Synopys has in terms of having tools for both manufacturing and design? As a follow-up, it appears that in the EDA business, critical mass is everything (the whole solution is greater than the sum of each tool), as tools need to operate with each other and be backward compatible. Can you comment on the advantages of economies of scale and how Synopsys expects to move forward?
A: Critical mass is a key theme in EDA today. Today, the demands of chip design are so inextricably linked that successful design requires a complete, comprehensive and correlated flow. The days of linking disparate, unrelated tools together into 'Frankenstein flows' are nearing their end. This strategy can no longer be successful because of the need for design tools to interact intimately at nanoscale geometries.
Since we were founded 21 years ago, we have always focused on the technology. We've been investing 25-30% of revenues into R&D until now, which is a pretty high ratio for the EDA industry, and in fact for the entire electronics industry.
Q: While Synopsys has commented that Moore's Law is progressing smoothly to 32nm, some players in the industry have commented that the industry needs to move beyond Moore's Law and focus more on trailing edge processes. However, Synopsys has chosen to pursue a leadership position on leading edge process design. Can you tell us about the risks and rewards of pursuing such a strategy? Does this mean Synopsys mostly focuses on companies that are targeting leading edge designs?
A: We track virtually ever advanced design in the world. We can do this because our Applications Engineers are involved in virtually every one of these designs, working to help make our customers successful. We have been tracking designs like this since 130 nanometers, and through the years, we have seen a very consistent migration to the next node every two years. 45/40nm is no different. It is tracking right in line with the previous nodes, and we expect the ramp to remain consistent.
We do work with semiconductor companies at the very leading edge, and help solve their hardest design problems. To do this successfully requires very strong collaboration, and we have focused in this area for some time. It is challenging to stay at the leading edge, but it is also rewarding as we continue on this journey with the leading semiconductor companies.
Customers all along the spectrum use our tools, flows and IP successfully. We recognize that the leading edge is just one segment of the market, so we put significant resources into helping ensure that our customers are successful regardless of whether they are on the leading edge, or taking advantage of the cost efficiencies at larger geometries.
Q: While it's true that design tools need to work well with IP and vice versa, Synopsys has been fairly unique that it has pursued both lines of business. Can you tell us how your IP business fits into your view of Technomics?
A: Since its inception, the mission of the EDA industry has been to improve the productivity of IC designers. This remains our focus. The massive number of transistors available to designers today is a strong techonomic consideration. Designers cannot be successful today designing all of a design's transistors from scratch. They must look outside their company to acquire standards- based IP that will help fill their transistor budget, and free their own designers to work on the value-added differentiators of the design. In this way, IP is a very logical extension of EDA and its mission of improving designer productivity.
Q: An increasing number of semiconductor players are looking to provide more system solution in the embedded space. Synopsys is targeting this market. Can you comment on your view of the embedded space and how you see it developing?
A: Embedded design has always been an important aspect of the design space. Today, as we embed more intelligence deeply into electronics in our every day environment, embedded design is increasing in importance. An important and rapidly growing aspect of embedded design is the software that runs on those designs. Designers must understand how their designs interact with that software early on, and software engineers need the capability to start their work before the silicon is available. This leads to the need for virtual prototypes and ASIC prototyping. We see a bright future for these two technologies.
Aart de Geus, CEO of electronic design automation (EDA) provider Synopsys
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