AMD will extend the roadmap for its 65nm-made Athlon 64 X2 CPU portfolio (codenamed Brisbane), with the series lineup adjusted to feature processor clock speeds differentiated by 100MHz, instead of the 200MHz, according to motherboard makers.
The adjusted clock speeds will be for parts including the Athlon 64 X2 4000+ (2.1GHz), Athlon 64 X2 4400+ (2.3GHz) and Athlon 64 X2 4800+ (2.5GHz), respectively, with the clock speeds splitting the difference between the 90nm existing models - Athlon 64 X2 3800+ and 4000+ (2.0GHz), Athlon 64 X2 4200+ and 4400+ (2.2GHz) and Athlon 64 X2 4600+ and 4800+ (2.4GHz).
The new 65nm Athlon 64 X2 processors will all appear with 2×512KB L2 cache memory, compared with 2×1MB for the similarly named 90nm versions, indicated the makers.
The 65nm CPU lineup has a TDP (thermal design point) of 65W, the makers added. The launch of the new 65nm Athlon 64 X2 CPU lineup will take place in November, the makers noted.
AMD will also add a 65nm version to the Athlon 64 X2 5000+ series, which is currently available in the 90nm Windsor version, the makers said. The 65nm part will have a TDP of 76W, according to the makers.
In addition, AMD will introduce the Athlon 64 X2 6000+ series (3GHz/2×1MB L2), manufactured using a 90nm process technology, in November, the makers said. The Athlon 64 X2 6000+ will be the renamed version of AMD's Athlon 64 FX family (FX-64), the makers added.
| AMD Athlon 64 X2 family (65nm Brisbane) | |||
| Model | Core speed | TDP | L2 cache |
| 5000+ | 2.6GHz | 76W | 2×512KB |
| 4800+ | 2.5GHz | 65W | |
| 4400+ | 2.3GHz | 65W | |
| 4000+ | 2.1GHz | 65W | |
Source: Motherboard makers, compiled by DigiTimes, September 2006
| AMD Athlon 64 X2 family (90nm Windsor) | |||
| Model | Core speed | TDP | L2 cache |
| 6000+ | 3.0GHz | 125W | 2×1MB |
| 5600+ | 2.8GHz | 89W | 2×1MB |
| 5400+ | 2.8GHz | 89W | 2×512KB |
| 5200+ | 2.6GHz | 89W | 2×1MB |
| 4600+ | 2.4GHz | 89W | 2×512KB |
| 4200+ | 2.2GHz | 89W | 2×512KB |
| 3800+ | 2GHz | 89W | 2×512KB |
Source: Motherboard makers, compiled by DigiTimes, September 2006
Article translated by Jessie Shen and edited by Michael McManus