Semiconductor design-service companies face any number of challenges as chip complexity rises in direct proportion to time-to-market pressure. Couple that with the industry’s move to deep submicron, and it soon becomes clear that IC design is not a business for the faint-hearted. Headquartered in Taiwan’s Hsinchu Science Park (HSP), EE Solutions is confronting the challenges with a commitment to design methodology, a determination to generate its own IP, a consistent focus on strategic markets and a sophisticated understanding bred of long experience in the industry.
DigiTimes.com spoke with EE Solutions president Jim Su and sales VP Hugh Huang about the company’s business model, the issues now facing the chip-design industry and the company’s strategy for success.
This is Part IV of a four-part interview. Part I appeared on 14 February, Part II on 15 February and Part III on 16 February.
Q: You indicated that tweaking the manufacturing process won’t necessarily enable successful designs at deep submicron. You also hinted that the reason why that approach won’t work is that there is a very high level of unpredictability at deep submicron. Am I understanding you correctly?
Su: Yes. Our response is to try to minimize the impact of the issue of manufacturability, the challenge of manufacturability at that scale.
From the point of view of our technology, we are continuing to innovate, while also implementing a very solid design methodology, to minimize the difficulties and challenges of nanometer-level designs. And we are also continuing to develop partnerships with some IC vendors, to develop the IP we need for deep submicron. But I want to emphasize that when we form those partnerships, we target certain specific markets. It’s not the case that we are going after every market segment.
Basically, there are two markets in which we would like to be involved. One is wireless communication, and specifically wireless LAN, and that also means MIMO and WiMAX. These are all areas where we are now engaging with customers. For example, we have a silicon-proven analog-to-digital converter (ADC), and the same ADC can be used for wireless LAN, in MIMO implementations, for WiMAX, and even in HDTV. That’s also an example of what I mean by repeatability – designs that can be repeated across a range of product applications.
An SoC can offer similar opportunities. An SoC will incorporate standard functionalities, such as memory, often a microprocessor, and possibly an analog-to digital/digital-to-analog converter (AD/DA), but you will also have, as a design company, some type of critical IP that enables you to complete the design.
So that’s our position, when we develop our technology. We start by building a very strong design methodology. Then we develop critical IP, for some very critical aspect of the design, and that enables us to develop the chips our customers and our target markets require. One of those markets is wireless, and another is digital entertainment. Wireless is a huge field, so we have to be selective. We don’t want to touch the videophone market, for example. That’s far too complicated, so we leave that one to Mediatek, or to TI, or whoever wants to do it. We only become involved in certain specific markets.
Another area where we can be involved is digital entertainment. You’ve got to have audio codecs, video codecs, and so on. So we have these critical pieces of the design, or perhaps a single piece, that enables us to do the design for our customers. If you want to understand our approach to design, there are two things we emphasize: a strong foundation in methodology; and critical IP that enables us to develop chips for customers.
Q: Do you ever sell IP?
Su: No. We develop it, but we don’t sell it.
Q: There’s not really a market for IP?
Su: If you look at the IP-design business, there’s really only one IP vendor that has managed to make an IPO, and that is ARM. Apart from ARM, most of them have either died or barely managed to survive. Only ARM has managed an IPO. IP is not a good business to get into. You can sell IP and do business that way, but it’s not scalable.
This is not a technology problem. The technology barrier is not really all that high. Let’s take USB 2.0 for example. Two years ago, you could sell a USB 2.0 chip design for US$300,000. Today, the same design would only fetch US$30,000. What happened is that people saw how profitable it was to design for USB 2.0. Their reaction was to get in on the act, and that had the effect of driving down prices. In the case of USB 1.1, I can’t even charge for it. Now, a USB 1.1 physical layer, for example, I give that away free to customers. Today, it wouldn’t be possible to sustain a chip-design operation based on meeting demand for USB chips. Of course, some companies will respond by developing their own niche specialization. They may decide to move to wireless USB, for example.
Another problem is collecting royalties. This is where ARM is very smart. They partner with the foundries, so they collect the royalties from either TSMC or UMC. The foundry gives ARM a report, so ARM knows how many wafers have been shipped.
It’s not easy to survive by selling IP, and we don’t sell IP. Our approach, rather, is to share the risks with the customer. We say, “Let’s work together and win together.” That means that when I work with you in putting a chip on the market, I need to have extremely good specifications for the chip, in order to satisfy customer demand. Then if the chip does well in the market, we sell the design to the customer, and both sides make money. This is the business model we prefer to operate.
Q: What is the future for EE Solutions and the industry? Can Moore's Law be sustained, and for how long?
Su: There are two points of view. One is that when you design at the nanometer level, you tend to count on technology provided by others. The foundry, for example, has to invest very large sums in technology for deep submicron, in acquiring the capability to go to 65 and 45 nanometers, and so on. This is from the process point of view. From the design point of view, the problem is that what works today may not work tomorrow at 65 and 45 nanometers. We have to look for a design breakthrough, a breakthrough in design, not simply in the process technology.
That means that the EDA industry can expect to see high levels of growth. There will be a large number of start-ups in the US, all looking at the process from different points of view. For example, I can give you at least ten examples of start-up companies in Silicon Valley who are developing DFM technology. Why? It’s because there is a demand, and the same applies to DFY. Some companies address these issues starting from RTL coding. Other people start from place and route; others start from routing. People are looking at these issues from different points of view, and all this is driven by Moore’s Law, of course.
This poses two major challenges for the industry. One of those issues is scalability. The industry will have to become very scalable. For example, let’s say there are now 500 fabless IC chip-design companies in China. They will inevitably face a lot of consolidation. There are going to be fewer fabless design companies. The second challenge is capital investment. How many companies can afford to continue to invest in fabs and foundries for fabrication at 300mm and 65 nanometers?
Recently I spoke with Princeton Technology Corporation (PTC), a very large company that last year shipped 400 million ICs, although most of those are consumer chips. Now that they are moving to deep submicron, they would be interested in partnering with us, to reduce their investment load. They want to reduce their investment in capital equipment and people, as they move into deep submicron. However, at 90 nanometers, you have to have a complete design team. It’s no longer a process that can be handled by individuals. At 0.35 micron, for example, one person could handle the EDA requirement, but that would not be the case at 90 nanometers.
So I think that on the one hand we will end up with a number of fabless companies, and on the other a number of system companies, whose major focus will be products for consumers. In between, they will need a company such as EE Solutions, which can provide services for both types of company. They will need to leverage our expertise, our resources and our investment. I can’t say exactly when this will happen, but I’m certain this will be the trend.
Q: So you are anticipating growth in the EDA industry?
Su: Yes. There are a lot of new entrants to the EDA industry. The past couple of years have been very slow for the EDA industry, but next year I think you will see a lot of new companies addressing the problems we have been talking about.
This is Part IV of a four-part interview. Part I appeared on 14 February, Part II on 15 February and Part III on 16 February.
Jim Su, president, EE Solutions Inc.
“Most of the founding members of the company have a background in EDA, so we have a strong background in design methodology.”
Article edited by Chris Hall
