ARM (Advanced RISC Machines) continues to turn the soft-IP business model into a success story. Last year saw the company undertake major acquisitions, and this year will see the arrival of a new Cortex applications processor core featuring Jazelle RCT and the v7 instruction set. ARM is on a growth curve, but while current financial results are healthy, ARM has plenty of competition, not least from configurable cores for the embedded space, such as those from Tensilica and ARC.
DigiTimes.com spoke in Taipei with ARM Marketing VP John Cornish about the company's plans, prospects, and future perspectives.
This is the first part of a two-part interview. Part II will follow on 15 August.
Q: Towards the end of last year, ARM announced a new architecture and a new set of cores, called Cortex. Can you detail the current status of this new architecture, its broad features, its availability, implementations to date and so on?
A: With the Cortex family, we are targeting a broad range of applications. Historically, ARM has developed families of microprocessors, with each family providing more performance than its predecessor. You saw that, for example, with the move from the ARM7 to the ARM9, and from ARM9 to the ARM10 and ARM11 families. So you can see there’s been a steady increase in performance, and we have added new features to those families, over time. For example, our DSP extensions were offered with our ARM 9E family, and Jazelle technology was first added with the ARM926EJ-S. Jazelle was then taken forward to the ARM10 and ARM11 families.
The Cortex cores are all compliant with the new v7 version of the architecture (the v7 instruction set and programmer’s model), and they are designed to address a range of applications, from low-end microcontrollers up to high-end consumer mobile applications. So very roughly, in performance terms, Cortex will offer clock speeds from below 100MHz to above 1GHz, and the Cortex family, as it is developed, will add new cores within this range, to serve the needs of different applications.
And in fact we have defined three profiles for v7. We have a microcontroller profile, v7M, and we have a real-time profile, v7R, and an applications profile, v7A. The M profile is used in the M series of products, so the first product in that family, the Cortex M3, which we announced last year, is designed for use in microcontrollers and effectively extends the range of the ARM7 offering to allow migration from 8-bit and 16-bit to proprietary designs. We also have in development, today, but not yet announced, a V7R real-time processor and a v7A applications processor. And over the next two or three years we will develop further Cortex cores, to meet the needs of different applications.
The Cortex applications processor design will scale to speeds above 1GHz, but we anticipate that many implementations will choose to run at lower voltages, for lower-power processes, at clock speeds between 600MHz and 700MHz. But the design is capable of running at above 1GHz, for applications that require that kind of speed.
We believe that the Cortex family will have a performance range that is unmatched by any of our competitors, and that’s important because many of our silicon partners are looking to standardize on a single architecture across a range of products. By providing this breadth of performance, we are able to meet their needs and enable them to standardize around ARM.
The other rationale behind the Cortex family and the v7 architecture is the recognition that many applications don’t actually a need a high level of performance, but they do need to have very efficient processors that are optimized for different performance points. So with v7 we are including Thumb-2, our latest technology for code density. Thumb-2 will be implemented on all Cortex cores. This allows us to offer greatly improved performance and code density for cores across that spectrum. So the Cortex M3, for example, implements Thumb-2 and will deliver better performance and code density than an ARM 7 TDMI.
This is really about offering architectural innovation across the performance range because we recognize that different applications have different requirements, and we need to have a range of products that meet those different needs.
We are also introducing some other technologies with Cortex, so the Jazelle Run-Time Compile Target (Jazelle RCT) will be implemented in the applications processors, the Cortex A series. Similarly, the NEON extensions, which we announced late last year, will be selectively implemented in the A- and R-series cores, with the R-series cores designed for real-time control. And then at the low end we have developed a new debug interface, called Serial Wire Debug or SWD. The SWD interface allows the cost of debug to be reduced because you can use just two pins to implement SWD, and this is especially important for low-cost devices targeting the microcontroller sectors. So the Cortex family includes several new technologies, and Thumb 2 is the common factor running through the family, with other technologies used in specific cores where appropriate.
We believe we have a very competitive range of processors, and for example with ARM11 we can deliver better performance, in a lower die size, at lower power. So by offering the ARM11 family, we can help to optimize our customers’ designs better than can our competitors.
Q: You made an interesting distinction between performance and the need for efficient processors at certain performance points. Can you amplify the distinction you are making here?
A: There are some applications where, for example, the ARM9 is simply the best choice. An ARM968E-S can run at up to 240MHz, but it consumes just 90K gates, plus SRAM, and that’s ideal for many networking applications – for 802.11 or WiMAX, for example. That’s about fitting the right processor core to the right type of application. And then of course there is ARM926EJ-S. This processor is capable of running open operating systems, such as Linux, as well as Windows CE. The ARM926EJ-S uses just 200K gates plus SRAM, and again runs at up to 250MHz on 0.13 micron. Again, this processor is ideal for many consumer applications – personal media players (PMPs) for example.
One interesting competitor comparison is the ARM11 versus the MIPS 24KE processor. In this case we can be up to 27% smaller, with the ARM1156T2-S, and we can use up to 53% less power, using ARM’s Intelligent Energy Manager (IEM) technology with the ARM11 MPCore processor.
Q: You mentioned that the Cortex architecture will incorporate a new variation of Jazelle, Jazelle RCT, which enhances the 16/32-bit Thumb-2 instruction set. Can you say more about Jazelle RCT in terms of features, implementation scenarios, performance gains, and so on?
A: The Jazelle RCT will be implemented in future Cortex cores, but we haven’t announced those cores yet. Essentially it is designed to improve the performance of JIT (Just in Time) and DAC (Dynamic Adaptive Compilation) compilers, so it can reduce the Java memory footprint by as much as three times. The Jazelle RCT includes new instructions that optimize the code density of JITs and DACs, and that’s very important in low-cost applications, where the amount of memory required is a key factor in the cost of the system.
We think that direct bytecode execution (DBX) will remain important for some time to come, and that’s what we have implemented, with Jazelle DBX, in the ARM926EJ and the ARM1136J-S. That is the existing technology we have implemented, but we need to extend that, using Jazelle RCT, to address the needs of JITs and DACs.
This is the first part of a two-part interview. Part II will follow on 15 August.
ARM Marketing VP John Cornish
Article edited by Chris Hall
